Operational cycle assignment in a configurable IC

• US 7,870,530 B2
• Filed: 08/18/2008
• Issued: 01/11/2011
• Est. Priority Date: 12/01/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Rohe, Andre, Teig, Steven
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): Sandoval, Patrick
• Application Number:
  US12/193,713
• Publication Number:
  US 20080307380A1
• Time in Patent Office: 876 Days
• Field of Search: 716/6, 716/16, 716/17
• US Class Current: 716/137
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and an end operation, the method assigns a particular operation in the first set to a first operational cycle based at least partially on the position of the particular operation with respect to the start and end operations.

Claims

1. A method of designing an integrated circuit (“

IC”

) with a plurality of reconfigurable circuits performing a plurality of configurable operations in a plurality of reconfigurable cycles, the method comprising;

receiving a design comprising a plurality of signal paths, each signal path having a source point and a target point and defined by a set of components communicatively coupled to each other, each component having an associated operation; and

for each particular component in a plurality of components, assigning the particular operation associated with the particular component to a particular reconfigurable circuit in a particular reconfigurable cycle based at least partially on a distance value computed for the particular component,

wherein each component in a group of components is only on one signal path,

wherein the distance value of each particular component in the group of components is (1) proportional to a signal delay from the source point of the particular component'"'"'s path to the particular component and (2) inversely proportional to a signal delay from the source point of the particular component'"'"'s signal path to the target point of the particular component'"'"'s signal path.

2. The method of claim 1, wherein the distance value for each particular component in the group of components is defined as the signal delay from the source point of the particular component'"'"'s signal path to the particular component divided by the signal delay from the source point of the particular component'"'"'s signal path to the target point of the particular component'"'"'s signal path.

3. The method of claim 1, wherein the distance value for each particular component in the group of components is further proportional to a number of intervening components between the source point of the particular component'"'"'s signal path to the particular component and inversely proportional to a number of intervening components between the source point of the particular component'"'"'s signal path to the target point of the particular component'"'"'s signal path.

4. The method of claim 1, wherein a signal delay between a first two consecutive components in a signal path is not equal to a signal delay between a second two consecutive components in the signal path.

5. The method of claim 1, wherein the distance value for each particular component in the group of components is a normalized topological metric value.

6. The method of claim 1, wherein the reconfigurable cycles are sub-cycles of a clock cycle.

7. The method of claim 1, wherein the assigning comprises assigning an approximately equal number of components to each of the plurality of reconfigurable cycles.

8. A non-transitory computer readable medium storing a computer program which when executed by at least one processor designs an integrated circuit (“

IC”

) with a plurality of reconfigurable circuits performing a plurality of configurable operations in a plurality of reconfigurable cycles, the computer program comprising;

a set of instructions for receiving a design comprising a plurality of signal paths, each signal path having a source point and a target point and defined by a set of components communicatively coupled to each other, each component having an associated operation; and

a set of instructions for assigning, for each particular component in a plurality of components, the particular operation associated with the particular component a particular reconfigurable circuit in a particular reconfigurable cycle based at least partially on a distance value computed for the particular component,

wherein each component in a group of components is only on one signal path,

wherein the distance value of each particular component in the group of components is (1) proportional to a signal delay from the source point of the particular component'"'"'s signal path to the particular component and (2) inversely proportional to a signal delay from the source point of the particular component'"'"'s signal path to the target point of the particular component'"'"'s signal path.

9. The non-transitory computer readable medium of claim 8, wherein the distance value for each particular component in the group of components is defined as the signal delay from the source point of the particular component'"'"'s signal path to the particular component divided by the signal delay from the source point of the particular component'"'"'s signal path to the target point of the particular component'"'"'s signal path.

10. The non-transitory computer readable medium of claim 8, wherein the distance value for each particular component in the group of components is further proportional to a number of intervening components between the source point of the particular component'"'"'s signal path to the particular component and inversely proportional to a number of intervening components from the source point of the particular component'"'"'s signal path to the target point of the particular component'"'"'s signal path.

11. The non-transitory computer readable medium of claim 8, wherein a signal delay between a first two consecutive components in a signal path is not equal to a signal delay between a second two consecutive components in the signal path.

12. The non-transitory computer readable medium of claim 8, wherein the distance value for each particular component in the group of components is a normalized topological metric value.

13. The non-transitory computer readable medium of claim 8, wherein the reconfigurable cycles are sub-cycles of a clock cycle.

14. The non-transitory computer readable medium of claim 8, wherein the assigning comprises assigning an approximately equal number of components to each of the plurality of reconfigurable cycles.

15. A method of designing an integrated circuit (“

IC”

) with a plurality of reconfigurable circuits performing a plurality of configurable operations in a plurality of reconfigurable cycles, the method comprising;

receiving a design comprising a plurality of signal paths, each signal path having a source point and a target point and defined by a plurality of components communicatively coupled to each other, each component having an associated operation; and

for each particular component in a plurality of components, assigning the particular operation associated with the particular component to a particular reconfigurable circuit in a particular reconfigurable cycle based at least partially on a distance value computed for the particular component,

wherein the distance value for the particular component is (1) proportional to a signal delay from the source point of a first signal path that includes the particular component to the particular component and (2) inversely proportional to a sum of a signal delay from the source point of the first signal path to the particular component and a signal delay from the particular component to the target point of a second signal path that includes the particular component.

16. The method of claim 15, wherein the first signal path is different from the second signal path.

17. The method of claim 15, wherein the first signal path is identical to the second signal path.