Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

• US 7,870,553 B2
• Filed: 01/11/2006
• Issued: 01/11/2011
• Est. Priority Date: 08/28/2003
• Status: Active Grant

• Current Assignee: MIPS Tech, LLC
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Kissell, Kevin D.
• Primary Examiner(s): Zhen, Li B
• Assistant Examiner(s): Kraft, Shih-Wei
• Application Number:
  US11/330,916
• Publication Number:
  US 20060190946A1
• Time in Patent Office: 1,826 Days
• Field of Search: None
• US Class Current: 718/102
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multiprocessing system is disclosed. The system includes a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler, coupled to the plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions of threads executing on the plurality of TCs. The system also includes a multiprocessor operating system (OS), configured to schedule execution of the threads on the plurality of TCs, wherein a thread of the threads executing on one of the plurality of TCs is configured to update the shared TLB, and prior to updating the TLB to disable interrupts, to prevent the OS from unscheduling the TLB-updating thread from executing on the plurality of TCs, and disable the instruction scheduler from dispatching instructions from any of the plurality of TCs except from the one of the plurality of TCs on which the TLB-updating thread is executing.

Claims

1. A multiprocessing system, comprising:

a multithreading microprocessor, comprising;

a first plurality of thread contexts;

a translation lookaside buffer (TLB), shared by said first plurality of TCs; and

an instruction scheduler, coupled to said first plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions of threads executing on said first plurality of TCs;

a multiprocessor operating system (OS), configured to schedule execution of said threads on said first plurality of TCs, wherein a thread of said threads executing on one of said first plurality of TCs is configured to update said shared TLB, and prior to updating said TLB to;

disable interrupts, to prevent said OS from unscheduling said TLB-updating thread from executing on said first plurality of TCs; and

disable said instruction scheduler from dispatching instructions from any of said first plurality of TCs except from said one of said first plurality of TCs on which said TLB-updating thread is executing;

wherein said multithreading microprocessor further comprises;

a virtual processing element (VPE), bound to said first plurality of TCs, wherein said VPE is an exception domain for said first plurality of TCs;

wherein said TLB-disabling thread disabling interrupts comprises disabling interrupts on said VPE;

wherein said multithreading microprocessor further comprises;

a second plurality of TCs; and

a second VPE, bound to said second plurality of TCs, wherein said second VPE is an exception domain for said second plurality of TCs;

wherein said TLB-disabling thread is further configured, prior to updating said shared TLB, to disable said instruction scheduler from dispatching instructions from any of said first and second plurality of TCs except from said one of said plurality of TCs on which said TLB-updating thread is executing; and

wherein said TLB-disabling thread is further configured, after updating said shared TLB, to restore said instruction scheduler to an instruction-dispatching state said instruction scheduler was in prior to disabling said instruction scheduler from dispatching instructions from any of said first and second plurality of TCs except from said one of said plurality of TCs on which said TLB-updating thread is executing.

2. The system as recited in claim 1, wherein said TLB-disabling thread is further configured, after updating said shared TLB, to restore said microprocessor to an interrupt-enabling state said microprocessor was in prior to disabling interrupts.

3. The system as recited in claim 1, wherein said shared TLB comprises a plurality of entries, each for caching a virtual to physical page address translation specified by one of a plurality of memory maps, wherein said OS is configured to create said plurality of memory maps for use by said first plurality of TCs executing a plurality of threads, wherein said OS is further configured to generate a plurality of address space identifiers (ASIDs) for identifying said plurality of memory maps, wherein each said TLB entry includes a tag comprising a virtual page address portion and an ASID portion, wherein said OS is configured to generate said plurality of ASIDs from a single ASID name space common to all of said first plurality of TCs.

4. The system as recited in claim 3, wherein said OS is further configured to generate said plurality of ASIDs from an ASID cache common to all of said first plurality of TCs.

5. The system as recited in claim 4, wherein said OS is configured to generate said plurality of ASIDs from said ASID cache by incrementing said ASID cache in a monotonically increasing manner.

6. The system as recited in claim 4, wherein said OS is further configured to grant one of said first plurality of TCs exclusive access to said ASID cache prior to generating each of said plurality of ASIDs.

7. The system as recited in claim 4, wherein said OS is further configured to serialize use and update of said ASID cache by each of the first plurality of TCs.

8. The system as recited in claim 7, wherein said OS serializing use and update of said ASID cache by each of the first plurality of TCs comprises:

disabling interrupts, to prevent said OS from unscheduling a thread updating said ASID cache from executing on said first plurality of TCs; and

disabling said instruction scheduler from dispatching instructions from any of said first plurality of TCs except from said one of said first plurality of TCs on which said ASID cache-updating thread is executing.

9. The system as recited in claim 8, wherein said ASID cache-disabling thread is further configured, after updating said ASID cache, to restore said instruction scheduler to an instruction-dispatching state said instruction scheduler was in prior to disabling said instruction scheduler from dispatching instructions from any of said first plurality of TCs except from said one of said first plurality of TCs on which said ASID cache-updating thread is executing.

10. The system as recited in claim 8, wherein said ASID cache-disabling thread is further configured, after updating said ASID cache, to restore said microprocessor to an interrupt-enabling state said microprocessor was in prior to disabling interrupts.

11. The system as recited in claim 4, wherein said OS is configured to maintain a table indicating which of said plurality of ASIDs generated by said OS is currently in use by said first plurality of TCs.

12. The system as recited in claim 11, wherein each of said first plurality of TCs comprises a register for storing an ASID value currently being used by said TC to identify one of said plurality of memory maps, wherein said OS is configured to maintain said table of in-use ASIDs by executing a thread on one of said first plurality of TCs to read said register from each of said first plurality of TCs.

13. The system as recited in claim 12, wherein said OS is configured to read said register from each of said first plurality of TCs to populate said table of in-use ASIDs in response to a rollover of said ASID cache to a new generation.

14. The system as recited in claim 13, wherein said OS is configured to flush said TLB in response to said rollover of said ASID cache to said new generation.

15. The system as recited in claim 13, wherein said OS is configured to generate a new ASID value in response to said rollover of said ASID cache to said new generation.

16. The system as recited in claim 11, wherein whenever said OS generates a new ASID from said ASID cache, said OS is configured to determine whether said new ASID is equal to one of said in-use ASID contained in said table, and if so, to generate another new ASID from said ASID cache until said new ASID is not equal to one of said in-use ASID contained in said table.

17. A method for a multiprocessor operating system (OS) to run on a multiprocessing system including a multithreading microprocessor having a first plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the first plurality of TCs, and an instruction scheduler configured to dispatch to execution units instructions of threads executing on the first plurality of TCs in a multithreaded fashion, the method comprising:

scheduling execution of the threads on the first plurality of TCs, wherein a thread of the threads executing on one of the first plurality of TCs is configured for updating the shared TLB;

disabling interrupts, prior to said updating the TLB, to prevent the OS from unscheduling the TLB-updating thread from executing on the first plurality of TCs;

disabling the instruction scheduler, prior to said updating the TLB, from dispatching instructions from any of the first plurality of TCs except from the one of the first plurality of TCs on which the TLB-updating thread is executing;

wherein the multithreading microprocessor further comprises a virtual processing element (VPE), bound to the first plurality of TCs, wherein the VPE is an exception domain for the first plurality of TCs, wherein said disabling interrupts further comprising disabling interrupts on the VPE;

wherein the multithreading microprocessor further comprises a second plurality of TCs and a second VPE, bound to the second plurality of TCs, wherein the second VPE is an exception domain for the second plurality of TCs, the method further comprising;

prior to updating the shared TLB, disabling the instruction scheduler from dispatching instructions from any of the first and second plurality of TCs except from the one of the plurality of TCs on which the TLB-updating thread is executing;

after updating the shared TLB, restoring the instruction scheduler to an instruction-dispatching state the instruction scheduler was in prior to disabling the instruction scheduler from dispatching instructions from any of the first and second plurality of TCs except from the one of the plurality of TCs on which the TLB-updating thread is executing.

18. The method as recited in claim 17, further comprising:

after updating the shared TLB, restoring the microprocessor to an interrupt-enabling state the microprocessor was in prior to disabling interrupts.

19. The method as recited in claim 17, wherein the shared TLB comprises a plurality of entries, each for caching a virtual to physical page address translation specified by one of a plurality of memory maps, the method further comprising:

creating the plurality of memory maps for use by the first plurality of TCs executing a plurality of threads; and

generating a plurality of address space identifiers (ASIDs) for identifying the plurality of memory maps, wherein each TLB entry includes a tag comprising a virtual page address portion and an ASID portion, wherein the OS is configured to generate the plurality of ASIDs from a single ASID name space common to all of the first plurality of TCs.

20. The method as recited in claim 19, further comprising:

generating the plurality of ASIDs from an ASID cache common to all of the first plurality of TCs.

21. The method as recited in claim 20, further comprising:

generating the plurality of ASIDs from the ASID cache by incrementing the ASID cache in a monotonically increasing manner.

22. The method as recited in claim 20, further comprising:

granting one of the first plurality of TCs exclusive access to the ASID cache prior to generating each of the plurality of ASIDs.

23. The method as recited in claim 20, further comprising:

serializing use and update of the ASID cache by each of the first plurality of TCs.

24. The method as recited in claim 23, wherein said serializing use and update of the ASID cache by each of the first plurality of TCs comprises:

disabling interrupts, to prevent the OS from unscheduling a thread updating the ASID cache from executing on the first plurality of TCs; and

disabling the instruction scheduler from dispatching instructions from any of the first plurality of TCs except from the one of the first plurality of TCs on which the ASID cache-updating thread is executing.

25. The method as recited in claim 24, further comprising:

after updating the ASID cache, restoring the instruction scheduler to an instruction-dispatching state the instruction scheduler was in prior to disabling the instruction scheduler from dispatching instructions from any of the first plurality of TCs except from the one of the first plurality of TCs on which the ASID cache-updating thread is executing.

26. The method as recited in claim 24, further comprising:

after updating the ASID cache, restoring the microprocessor to an interrupt-enabling state the microprocessor was in prior to disabling interrupts.

27. The method as recited in claim 20, further comprising:

maintaining a table indicating which of the plurality of ASIDs generated by the OS is currently in use by the first plurality of TCs.

28. The method as recited in claim 27, wherein each of the first plurality of TCs comprises a register for storing an ASID value currently being used by the TC to identify one of the plurality of memory maps, the method further comprising:

maintaining the table of in-use ASIDs by executing a thread on one of the first plurality of TCs to read the register from each of the first plurality of TCs.

29. The method as recited in claim 28, further comprising:

reading the register from each of the first plurality of TCs to populate the table of in-use ASIDs in response to a rollover of the ASID cache to a new generation.

30. The method as recited in claim 29, further comprising:

flushing the TLB in response to the rollover of the ASID cache to the new generation.

31. The method as recited in claim 29, further comprising:

generating a new ASID value in response to the rollover of the ASID cache to the new generation.

32. The method as recited in claim 27, further comprising:

whenever the OS generates a new ASID from the ASID cache, determining whether the new ASID is equal to one of the in-use ASID contained in the table; and

if so, generating another new ASID from the ASID cache until the new ASID is not equal to one of the in-use ASID contained in the table.

33. A computer program product for use with a computing device, the computer program product comprising:

a computer readable storage medium, having computer readable program code embodied in said computer readable storage medium, for causing a method for method for a multiprocessor operating system (OS) to run on a multiprocessing system including a multithreading microprocessor having a first plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the first plurality of TCs, and an instruction scheduler configured to dispatch to execution units instructions of threads executing on the first plurality of TCs in a multithreaded fashion, said computer readable program code comprising;

first program code for providing a step of scheduling execution of the threads on the first plurality of TCs, wherein a thread of the threads executing on one of the first plurality of TCs is configured for updating the shared TLB;

second program code for providing a step of disabling interrupts, prior to said updating the TLB, to prevent the OS from unscheduling the TLB-updating thread from executing on the first plurality of TCs; and

third program code for providing a step of disabling the instruction scheduler, prior to said updating the TLB, from dispatching instructions from any of the first plurality of TCs except from the one of the first plurality of TCs on which the TLB-updating thread is executing;

wherein the multithreading microprocessor further comprises a virtual processing element (VPE), bound to the first plurality of TCs, wherein the VPE is an exception domain for the first plurality of TCs, wherein said second program code for providing a step of disabling interrupts comprises disabling interrupts on the VPE;

wherein the multithreading microprocessor further comprises a second plurality of TCs and a second VPE, bound to the second plurality of TCs, wherein the second VPE is an exception domain for the second plurality of TCs, the third program code for providing a step of disabling the instruction scheduler further comprises;

prior to updating the shared TLB disabling the instruction scheduler from dispatching instructions from any of the first and second plurality of TCs except from the one of the plurality of TCs on which the TLB-updating thread is executing;

fourth program code for providing a step of, after updating the shared TLB, restoring the instruction scheduler to an instruction-dispatching state the instruction scheduler was in prior to disabling the instruction scheduler from dispatching instructions from any of the first and second plurality of TCs except from the one of the plurality of TCs on which the TLB-updating thread is executing.