Shielded gate trench FET with an inter-electrode dielectric having a nitride layer therein

• US 7,872,305 B2
• Filed: 06/26/2008
• Issued: 01/18/2011
• Est. Priority Date: 06/26/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Hunt, Scott L.
• Primary Examiner(s): Pham; Hoai v
• Application Number:
  US12/146,791
• Publication Number:
  US 20090321817A1
• Time in Patent Office: 936 Days
• Field of Search: 257/330, 257/331, 257/332, 257/E27.091
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A shielded gate field effect transistor (FET) comprises a plurality of trenches extending into a semiconductor region. A shield electrode is disposed in a bottom portion of each trench, and a gate electrode is disposed over the shield electrode in each trench. An inter-electrode dielectric (IED) extends between the shield electrode and the gate electrode. The IED comprises a first oxide layer and a nitride layer over the first oxide layer.

Claims

1. A shielded gate field effect transistor (FET), comprising:

a plurality of trenches extending into a semiconductor region;

a shield electrode in a bottom portion of each trench;

a gate electrode over the shield electrode; and

an inter-electrode dielectric (IED) extending between the shield electrode and the gate electrode, the IED comprising;

(i) a first oxide layer, and

(ii) a nitride layer over the first oxide layer.

2. The shielded gate FET of claim 1 wherein the semiconductor region further comprises:

a drift region of a first conductivity type extending over a substrate, the substrate having a higher doping concentration than the drift region;

a body region of a second conductivity type extending over the drift region; and

source regions of the first conductivity type adjacent to each trench in the body region, wherein the plurality of trenches extend into and terminate within the drift region.

3. The shielded gate FET of claim 1 wherein the semiconductor region further comprises:

a drift region of a first conductivity type extending over a substrate, the substrate having a higher doping concentration than the drift region;

a body region of a second conductivity type extending over the drift region; and

source regions of the first conductivity type adjacent to each trench in the body region, wherein the plurality of trenches extend into and terminate within the substrate.

4. The shielded gate FET of claim 1 further comprising:

a shield dielectric lining lower sidewalls and a bottom of each trench, wherein top surfaces of the shield dielectric are recessed relative to a top surface of the shield electrode so as to form recesses adjacent to opposing sides of the shield electrode, and wherein the first oxide layer and the nitride layer fill the recesses.

5. The shielded gate FET of claim 4 wherein the first oxide layer and the nitride layer overlap the shield electrode along a depth of the plurality of trenches.

6. The shielded gate FET of claim 1 further comprising:

a gate dielectric extending between the gate electrode and the semiconductor region, the gate dielectric comprising;

(i) the first oxide layer, and

(ii) the nitride layer over the first oxide layer.

7. The shielded gate FET of claim 6 wherein the nitride layer in the IED and in the gate dielectric are contiguous.

8. The shielded gate FET of claim 6 wherein the nitride layer is thicker than the first oxide layer.

9. The shielded gate FET of claim 6 wherein the nitride layer is thinner than the first oxide layer.

10. The shielded gate FET of claim 6 wherein a thickness of the first oxide layer in the IED is greater than a thickness of the first oxide layer in the gate dielectric.

11. The shielded gate FET of claim 6 wherein the gate dielectric further comprises a second oxide layer vertically extending between the gate electrode and the nitride layer.

12. The shielded gate FET of claim 11 wherein the second oxide layer also forms part of the IED and extends over the nitride layer.

13. The shielded gate FET of claim 12 wherein the second oxide layer in the IED and in the gate dielectric are contiguous.

14. The shielded gate FET of claim 13 wherein the first oxide layer is thicker than the second oxide layer.

15. A shielded gate field effect transistor (FET), comprising:

a plurality of trenches extending into a semiconductor region;

a shield electrode in a bottom portion of each trench;

a gate electrode over the shield electrode; and

an inter-electrode dielectric (IED) extending between the shield electrode and the gate electrode, the IED comprising;

(i) a first oxide layer, and

(ii) a nitride layer over the first oxide layer, wherein the nitride layer laterally extends between the shield electrode and the gate electrode, the nitride layer having outer portions that extend downward.

16. The shielded gate FET of claim 15 wherein the outer portions of the nitride layer that extend downward overlap the shield electrode along a depth of the plurality of trenches.

17. The shielded gate FET of claim 15 further comprising:

a shield dielectric lining lower sidewalls and a bottom of each trench, wherein top surfaces of the shield dielectric are recessed relative to a top surface of the shield electrode so as to form recesses adjacent to opposing sides of the shield electrode, and wherein the outer portions of the nitride layer that extend downward fill the recesses.

18. The shielded gate FET of claim 15 further comprising:

a gate dielectric extending between the gate electrode and the semiconductor region, the gate dielectric comprising;

(i) the first oxide layer, and

(ii) the nitride layer over the first oxide layer.

19. The shielded gate FET of claim 18 wherein the nitride layer in the IED and in the gate dielectric are contiguous.

20. The shielded gate FET of claim 18 wherein a thickness of the first oxide layer in the IED is greater than a thickness of the first oxide layer in the gate dielectric.

21. The shielded gate FET of claim 18 wherein the gate dielectric further comprises a second oxide layer vertically extending between the gate electrode and the nitride layer.

22. The shielded gate FET of claim 21 wherein the IED further comprises the second oxide layer over the nitride layer.

23. The shielded gate FET of claim 22 wherein the second oxide layer in the IED and in the gate dielectric are contiguous.

24. The shielded gate FET of claim 23 wherein the first oxide layer is thicker than the second oxide layer.