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Microelectronic assemblies having compliant layers

  • US 7,872,344 B2
  • Filed: 06/23/2006
  • Issued: 01/18/2011
  • Est. Priority Date: 10/31/1995
  • Status: Expired due to Fees
First Claim
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1. A compliant semiconductor chip package assembly comprising:

  • a semiconductor chip having a major surface and plurality of chip contacts at said major surface;

    a compliant layer having a bottom surface adjacent to said major surface, a top surface raised above and remote from said major surface and at least a first sloping peripheral edge between said top and bottom surfaces, wherein the bottom surface of the compliant layer overlies a surface of the semiconductor chip and at least a portion of the bottom surface of the compliant layer is remote from the chip contacts; and

    a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, said traces extending along the first sloping edge to the top surface of the compliant layer.

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