Identifying and accessing individual memory devices in a memory channel
First Claim
1. In a memory module with a plurality of memory integrated circuits providing a Unified Memory Architecture (UMA), each of the plurality of memory integrated circuits having at least two pins to couple information into each of the memory integrated circuits, method comprising:
- setting values of at least two identity bits respectively onto the at least two pins of each memory integrated circuit of the UMA;
receiving the at least two identity bits into each memory integrated circuit of the UMA as an identity value;
using a data qualifier to individually program each of the memory integrated circuits with the at least two identity bits, wherein accesses into each memory integrated circuit are micro-tile memory accesses utilizing at least the two identity bits, wherein the micro-tile memory accesses comprise independent sub-channel memory accesses into the at least one memory integrated circuit;
retrieving data from at least one of the memory integrated circuits via the independent sub-channel memory accesses; and
returning a cache line having the retrieved data, wherein the retrieved data comprises data from discontiguous memory locations as a single cache line.
2 Assignments
0 Petitions
Accused Products
Abstract
In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.
32 Citations
15 Claims
-
1. In a memory module with a plurality of memory integrated circuits providing a Unified Memory Architecture (UMA), each of the plurality of memory integrated circuits having at least two pins to couple information into each of the memory integrated circuits, method comprising:
-
setting values of at least two identity bits respectively onto the at least two pins of each memory integrated circuit of the UMA; receiving the at least two identity bits into each memory integrated circuit of the UMA as an identity value; using a data qualifier to individually program each of the memory integrated circuits with the at least two identity bits, wherein accesses into each memory integrated circuit are micro-tile memory accesses utilizing at least the two identity bits, wherein the micro-tile memory accesses comprise independent sub-channel memory accesses into the at least one memory integrated circuit; retrieving data from at least one of the memory integrated circuits via the independent sub-channel memory accesses; and returning a cache line having the retrieved data, wherein the retrieved data comprises data from discontiguous memory locations as a single cache line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A Unified Memory Architecture (UMA) comprising a plurality of memory integrated circuits, each memory integrated circuit including:
-
a memory array to store data; a register including one or more bit storage circuits to store one or more identity bits; and control logic coupled to the register, the control logic to provide independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register, wherein the register of each memory integrated circuit in the UMA is individually programmed using a data qualifier, and the one or more identity bits are one or more sub-channel select bits, the control logic further to retrieve data from the memory array via the independent sub-channel memory accesses return a cache line having the retrieved data, wherein the retrieved data comprises data from discontiguous memory locations as a single cache line. - View Dependent Claims (14, 15)
-
Specification