Non-volatile semiconductor memory with page erase

• US 7,872,921 B2
• Filed: 05/28/2009
• Issued: 01/18/2011
• Est. Priority Date: 03/29/2006
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): Lam; David
• Application Number:
  US12/474,056
• Publication Number:
  US 20090231928A1
• Time in Patent Office: 600 Days
• Field of Search: 365/185.29, 36518517-18518, 365/185.27, 365/185.23, 365/185.12, 365/185.22
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

In a nonvolatile memory, less than a full block may be erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.

Claims

1. A method for verifying erase of pages of non-volatile memory array having n blocks, each block having m pages of memory cells, each of n and m being a positive integer, one or more pages being selected in a selected block, each block having a plurality of strings of memory cells on a substrate and m wordlines across the strings, each wordline being operably connected to a respective one of the m pages of memory cells, the method comprising:

connecting each of the strings to a common source line voltage; and

selecting a level of the common source line voltage from a plurality of voltage levels dependent on a number of the of selected word lines;

applying a select verify voltage to each wordline corresponding to the selected one or more pages for causing each memory cell of the selected one or more pages to conduct only if erased;

applying an unselect verify voltage to each wordline corresponding to the unselected pages for causing each memory cell of the unselected pages to conduct regardless of a respective state of each memory cell of the unselected pages; and

sensing a state of each string for verifying erase of each memory cell of each selected wordline.

2. The method as claimed in claim 1, wherein applying a select verify voltage comprises applying 0 volts to each of the wordlines corresponding to the selected pages.

3. The method as claimed in claim 1, wherein applying the unselect verify voltage comprises applying a read voltage to each of the wordlines corresponding to the unselected pages.

4. A method for verifying erase of pages of non-volatile memory array having n blocks, each block having m pages of memory cells, each of n and m being a positive integer, one or more pages being selected in a selected block, each block having a plurality of strings of memory cells on a substrate and m wordlines across the strings, each wordline being operably connected to a respective one of the m pages of memory cells, the method comprising:

connecting each of the strings to a common source line voltage; and

selecting a level of the common source line voltage from a plurality of voltage levels, wherein a number of the plurality of voltage levels is substantially less than m−

1;

applying a select verify voltage to each wordline corresponding to the selected one or more pages for causing each memory cell of the selected one or more pages to conduct only if erased;

applying an unselect verify voltage to each wordline corresponding to the unselected pages for causing each memory cell of the unselected pages to conduct regardless of a respective state of each memory cell of the unselected pages; and

sensing a state of each string for verifying erase of each memory cell of each selected wordline.

5. A non-volatile memory comprising a memory array having a plurality of blocks, each block comprising:

m pages of memory cells, m being a positive integer

a plurality of strings of memory cells on a substrate, and

m wordlines across the strings, each of the wordlines being operably connected to a respective one of the m pages,

the memory further comprising;

a voltage applier for applying;

a select verify voltage to the wordline of an erased page in a selected block, and

an unselect verify voltage to the wordline of a non-erased page in the selected block; and

sensors for sensing states of the strings;

wherein each of the strings is connectable to a common source line voltage, a level of the common source line voltage being selectable from one of a plurality of voltage levels dependent on a number of the plurality of erased pages.

6. A non-volatile memory as claimed in claim 5, wherein the level of he common source line voltage is selected to be substantially within a range of r=0.3 to 0.5 volts if the number of the plurality of erased pages is one.

7. A non-volatile memory as claimed in claim 6, wherein the selected level of the common source line voltage is reduced by r/m for each additional erased page.

8. A non-volatile memory as claimed in claim 6, wherein the selected level of the common source line voltage is reduced as the number of the plurality of erased pages increases.

9. A non-volatile memory as claimed in claim 5 wherein the voltage applier comprises:

a voltage provider for providing the select verify voltage and the unselect verify voltage in response to an address instruction.

10. A non-volatile memory as claimed in claim 9 wherein the voltage provider comprises:

a latch for latching a logic condition in response to the address instruction.

11. A non-volatile memory as claimed in claim 10 wherein the voltage applier further comprises:

a pass transistor for passing the select verify voltage to the wordline of the erased page.

12. A non-volatile memory as claimed in claim 5 wherein the select verify voltage causes each memory cell of the selected one or more pages to conduct only if erased and the unselect verify voltage causes each memory cell of the unselected pages to conduct regardless of a respective state of each memory cell of the unselected pages.

13. A method of verifying erase of one or more pages in a non-volatile memory array having plural strings of memory cells on the substrate and word lines across the strings to pages of memory cells, the method comprising:

to each of plural selected word lines of a selected block, applying a select verify voltage that causes each memory cell to conduct only if erased;

to each of plural unselected word lines of the selected block, applying an unselect verify voltage that causes each memory cell to conduct regardless of state; and

sensing state of each string to verify erase of each memory cell of each selected word line;

wherein each string is connected to an end voltage, the level of the end voltage being selected from one of plural voltage levels dependent on the number of selected word lines.

14. A non-volatile memory comprising:

a memory array comprising plural strings of memory cells on a substrate and word lines across the strings to pages of memory cells;

a word line decoder that applies a select verify voltage to each word line of plural erased pages in a selected block and an unselect verify voltage to each word line of plural non-erased pages in the selected block; and

sensors that sense state of strings of the selected block;

wherein each string is connected to an end voltage, the level of the end voltage being selected from one of plural voltage levels dependent on the number of selected word lines.

15. A non-volatile memory as claimed in claim 14 wherein the select verify voltage causes each memory cell to conduct only if erased and the unselect verify voltage causes each memory cell to conduct regardless of state.