Semiconductor memory device and method of controlling power source

• US 7,872,927 B2
• Filed: 09/27/2006
• Issued: 01/18/2011
• Est. Priority Date: 09/27/2005
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Takeda, Koichi
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US12/067,265
• Publication Number:
  US 20100149887A1
• Time in Patent Office: 1,574 Days
• Field of Search: 365/189.16, 365/185.05
• US Class Current: 365/189.16
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A voltage generator that monitors a writing margin as a control amount in order to carry out an optimum power source control when control of a SRAM cell power source is carried out at writing operation, and always keeps the writing margin constant; and a power source selector are included to switch power source voltage at writing. By switching the power source voltage at writing, a semiconductor memory device in which a stable writing operation is achieved without largely deteriorating writing time in the SRAM cell and an ultrahigh speed operation or ultralow power operation can be carried out is obtained.

Claims

1. A semiconductor memory device comprising a writing margin monitoring circuit, the writing margin monitoring circuit comprising a simulation circuit in which a replicated load transistor and a replicated access transistor are connected in series, the replicated load transistor and the replicated access transistor respectively simulating a load transistor and an access transistor of a SRAM cell so that a current flowing to the access transistor that discharges a potential of a storage node of the SRAM cell equals a current flowing to the load transistor of the SRAM cell at a writing operation.

2. The semiconductor memory device as claimed in claim 1, wherein the writing margin monitoring circuit further comprises a second replicated load transistor, a replicated inverter circuit constructed from a replicated drive transistor and an operational amplifier, the replicated inverter circuit outputs a second output signal when a first output signal is inputted from the simulation circuit, the first output signal and the second output signal are inputted to the operational amplifier, and an output signal of the operational amplifier that is an output signal of the writing margin monitoring circuit is outputted as gate voltage of the replicated access transistor.

3. The semiconductor memory device as claimed in claim 2, wherein voltage of the first output signal is equal to threshold value voltage of first and second inverters that configure the SRAM cell and are loop-connected.

4. The semiconductor memory device as claimed in claim 2, wherein each of the replicated load transistor and the second replicated load transistor is constructed from a transistor having the same characteristic as that of the load transistor that configures the SRAM cell, the replicated access transistor is constructed from a transistor having the same characteristic as that of the access transistor that configures the SRAM cell, and the replicated drive transistor is constructed from a transistor having the same characteristic as that of a drive transistor that configures the SRAM cell.

5. The semiconductor memory device as claimed in claim 2, wherein an output signal from a node at which a second replicated access transistor is connected to a second replicated drive transistor in series is inputted to a gate of the replicated load transistor.

6. The semiconductor memory device as claimed in claim 2, wherein low power source voltage is inputted to a gate of the replicated load transistor.

7. The semiconductor memory device as claimed in claim 1, further comprising a voltage generator and a power source selector, wherein the power source selector switches second high power source voltage or second low power source voltage generated by the voltage generator to apply it as a power source of the SRAM cell at writing.

8. The semiconductor memory device as claimed in claim 7, wherein the voltage generator outputs the second power source voltage or the second low power source voltage by controlling an output transistor by means of an output of an operational amplifier to which reference voltage that is lowered by margin voltage from high power source voltage and output voltage from the writing margin monitoring circuit are inputted.

9. The semiconductor memory device as claimed in claim 1, wherein the writing margin monitoring circuit further comprises a second replicated load transistor, a replicated inverter circuit constructed from a replicated drive transistor, an operational amplifier and a voltage generator, the replicated inverter circuit outputs a second output signal when a first output signal is inputted from the simulation circuit, the first output signal and the second output signal are inputted to the operational amplifier, and the voltage generator outputs second high power source voltage or second low power source voltage by controlling an output transistor by means of an output signal from the operational amplifier.

10. The semiconductor memory device as claimed in claim 9, wherein reference voltage that is lowered by margin voltage from high power source voltage is inputted to a gate of the replicated access transistor.

11. The semiconductor memory device as claimed in claim 9, wherein either the second high power source voltage and low power source voltage or high power source voltage and the second low power source voltage are applied as a power source of the replicated inverter circuit.

12. The semiconductor memory device as claimed in claim 9, further comprising a power source selector, wherein the power source selector switches the second high power source voltage or the second low power source voltage to apply it as a power source of the SRAM cell at writing.

13. A method of controlling a power source of a semiconductor memory device, the semiconductor memory device comprising a simulation circuit, a replicated inverter circuit, an operational amplifier, a voltage generator and a power source selector, the simulation circuit being constructed from a replicated load transistor and a replicated access transistor that respectively simulate a load transistor and an access transistor that configure a SRAM cell, the replicated inverter circuit being constructed from second replicated load transistor and replicated drive transistor to which an output from the simulation circuit is inputted, outputs from the simulation circuit and the replicated inverter circuit being inputted to the operational amplifier, the voltage generator generating second high power source voltage or second low power source voltage by means of an output from the operational amplifier, wherein when a writing instruction is inputted, the power source selector applies either the second high power source voltage and low power source voltage or high power source voltage and the second low power source voltage as a power source of the SRAM cell.

14. The method of controlling the power source of the semiconductor memory device as claimed in claim 13, wherein when a writing instruction is inputted, the power source selector applies the second high power source voltage and the low power source voltage or the high power source voltage and the second low power source voltage as a power source of the replicated inverter circuit.