Method of design analysis of existing integrated circuits

• US 7,873,203 B2
• Filed: 08/29/2008
• Issued: 01/18/2011
• Est. Priority Date: 08/31/2004
• Status: Active Grant

• Current Assignee: TechInsights, Inc. (M3, Inc.)
• Original Assignee: Semiconductor Insights Incorporated (Informa PLC)
• Inventors: Begg, Stephen, Gont, Val, Abt, Jason, Keyes, Edward, Zavadsky, Vyacheslav L.
• Primary Examiner(s): Mehta; Bhavesh M
• Assistant Examiner(s): RAHMJOO, MANUCHEHR
• Application Number:
  US12/200,975
• Publication Number:
  US 20080317328A1
• Time in Patent Office: 872 Days
• Field of Search: 382/141, 382/140, 382/144, 382/145, 382/147, 382/149
• US Class Current: 382/141
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/001 using an image reference approach
• CPC Class Codes: G06T 7/74 involving reference images or patches

Abstract

The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

Claims

1. A method of determining possible locations of standard cells in an image of an IC layout, comprising the following steps, implemented using a processor having access to the image, of:

extracting points of interest from the image;

creating a descriptor in the vicinity of each of the points of interest, wherein the descriptor comprises a grid having a number of non-overlapped rectangles, said non-overlapped rectangles represented by a first bit if they contain at least a predetermined percentage of the first conductive layer and represented by a second bit if they contain less than the predetermined percentage;

extracting a first instance of a standard cell from the image;

comparing descriptors from the first instance of a standard cell to the other descriptors of the image to identify similar points of interest;

casting votes on the similar points of interest to show the level of confidence on the similarity of the similar points of interest; and

computing the weight of the votes and determining possible matches by locations on the image showing high weights.

2. A method as claimed in claim 1 wherein said points of interest comprise centers of contacts on a first conductive layer of the IC.

3. A method as claimed in claim 1 wherein said points of interest comprise centers of vias on a first conductive layer of the IC.

4. A method as claimed in claim 1 wherein said points of interest comprise corners of polygons representing a first conductive layer of the IC.

5. A method as claimed in claim 1 wherein the descriptor is a 32-bit bitmap descriptor.

6. A method as claimed in claim 1 wherein the descriptors from the first instance of a standard cell comprise eight possible orientations of the standard cell.

7. Apparatus for determining possible locations of standard cells in an image of an IC layout comprising:

a processor having access to said image and comprising;

means for extracting points of interest from the image;

means for creating a descriptor in the vicinity of each of the points of interest, wherein the descriptor comprises a grid having a number of non-overlapped rectangles, said non-overlapped rectangles represented by a first bit if they contain at least a predetermined percentage of a first conductive layer of the IC and represented by a second bit if they contain less than the predetermined percentage;

means for extracting a first instance of a standard cell from the image;

means for comparing descriptors from the first instance of a standard cell to the other descriptors of the image to identify similar points of interest;

means for casting votes on the similar points of interest to show the level of confidence on the similarity of the similar points of interest; and

means for computing the weight of the votes and determining possible matches by locations on the image showing high weights.

8. Apparatus as claimed in claim 7 wherein the points of interest are selected from centers of contacts on a first conductive layer of the IC, centers of vias on the first conductive layer and corners of polygons representing the first conductive layer.

9. Apparatus as claimed in claim 7 wherein the descriptor is a 32-bit bitmap descriptor.

10. Apparatus as claimed in claim 7 wherein the descriptors from the first instance of a standard cell comprise eight possible orientations of the standard cell.