Multiple processor system and method including multiple memory hub modules

• US 7,873,775 B2
• Filed: 07/20/2009
• Issued: 01/18/2011
• Est. Priority Date: 08/28/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): Rinehart; Mark
• Assistant Examiner(s): Cerullo; Jeremy S
• Application Number:
  US12/505,933
• Publication Number:
  US 20090282182A1
• Time in Patent Office: 547 Days
• Field of Search: 710/317, 711/117, 711/170
• US Class Current: 710/317
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00

Abstract

A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

Claims

1. A memory system, comprising:

a plurality of memory requestors; and

a first rank containing a plurality of memory modules each of which comprises;

a plurality of memory devices;

a memory hub coupled to a plurality of the memory requestors, to a port, and to the memory devices in the memory module, the memory hub in each of the memory modules being configured to allow any of the memory requesters to access the memory devices to which it is coupled and to communicate with the port of the memory hub; and

a second rank containing a plurality of memory modules each of which comprises;

a plurality of memory devices; and

a memory hub coupled to the memory devices in the memory module and to the respective port of the memory hub in each of a plurality of the memory modules in the first rank, the memory hub in each of the memory modules in the second rank being configured to allow any of the memory requestors to access the memory devices to which it is coupled through at least one memory module in the first rank.

2. The memory system of claim 1 wherein the memory hub in each of the memory modules in the second rank includes a plurality of memory ports corresponding in number to the number of memory modules in the first rank, the memory ports in the memory hub in each of the memory modules in the second rank being coupled to the memory modules in the first rank through respective ones of the memory ports.

3. The memory system of claim 1 wherein the memory hub in each of the memory modules in the first rank comprise a cross bar switch operable to couple any of the memory requesters to any of the memory devices to which it is connected and to the memory hub in any of the memory modules in the second set.

4. A memory system, comprising:

a plurality of memory requestors;

a first rank of memory modules each of which is coupled to the plurality of memory requesters, each of the memory modules in the first rank comprising a plurality of memory devices and being configured to allow any of the memory requestors to which it is coupled to selectively access the memory device in the memory module, the memory module further comprises a port configured to selectively communicate with any of the memory requestors to which the memory module is coupled; and

a second rank of memory modules each of which is coupled to the memory modules in the first rank through the respective ports of the memory modules in the first rank, each of the memory modules in the second rank comprising a plurality of memory devices and being configured to allow any of the memory requestors to selectively access the memory device in the memory module through at least one of the memory modules in the first rank.

5. The memory system of claim 4 wherein each of the memory devices comprises a dynamic random access memory device.

6. The memory system of claim 4 wherein each of the memory modules further comprises a respective cache memory device.

7. The memory system of claim 4 wherein each of the memory modules further comprises a respective write buffer configured to receive write data and associated write addresses from each of the memory requesters and to store the write data and addresses for subsequent coupling to at least some of the memory device in the memory module.

8. The memory system of claim 7 wherein each of the write buffers is configured to accumulate write data and addresses for a plurality of write memory accesses and then sequentially couple the plurality of write data and addresses to at least some of the memory devices in the memory module without any intervening read memory accesses.

9. The memory system of claim 4 wherein each of the memory modules further comprise a direct memory access device configured to access at least some of the memory device in the memory module.

10. The memory system of claim 4 wherein at least some of the memory requesters comprise a processor.

11. The memory system of claim 4 wherein at least some of the memory requesters comprise a direct memory access device.

12. A system, comprising:

a plurality of memory requestors;

a first rank of memory modules coupled to the memory requestors, the memory modules in the first rank each including a first set of memory ports coupled to a respective one of the memory requestors, the memory modules in the first rank further including a second set of memory ports, each of the memory modules in the first rank including a plurality of memory devices; and

a second rank of memory modules each including at least one memory port coupled to a memory module in the first rank through a memory port in the second set, each of the memory modules in the second rank including a plurality of memory devices, each of the memory modules in the second rank being accessed by at least one of the memory requestors through at least one of the memory modules in the first rank, the memory modules in the first set being configured to allow the number of memory modules in the first rank through which the at least one memory module in the second rank is accessed to be adjustable to vary the data bandwidth between the at least one memory requestor and the at least one memory module in the second rank.

13. The system of claim 12 wherein the number of ports in the second set of each of the memory modules in the second rank corresponds in number to the number of modules in the first rank.

14. The system of claim 12 wherein the number of ports in the first set of each of the memory modules in the first rank corresponds in number to the number of memory requestors.

15. A system, comprising;

a plurality of memory requestors;

a first rank of memory modules coupled to the memory requestors, the memory modules in the first rank each including a first set of memory ports corresponding in number to the number of memory requestors, each of the memory ports in the first rank being coupled to a respective one of the memory requestors, the memory modules in the first rank further including a second set of memory ports, each of the memory modules in the first rank including a plurality of memory devices; and

a second rank of memory modules each including a plurality of memory devices and at least one memory port coupled to a memory module in the first rank through a memory port in the second set, each of the memory modules in the second rank being accessed by at least one of the memory requestors through at least one of the memory modules in the first rank.

16. The system of claim 15 wherein each of the memory modules in the second rank includes a plurality of memory ports corresponding in number to the number of memory modules in the first rank, the memory ports in each of the memory modules in the second rank being coupled to the memory modules in the first rank through respective memory ports in the second set.

17. The system of claim 15 wherein each of a plurality of sets of memory modules in the second rank are coupled to a respective one of the memory modules in the first rank, each of the memory modules in the first rank including a memory port coupled to the memory module in the first rank to which the respective set of memory modules in the second rank corresponds.