Nonvolatile memory with self recovery

• US 7,873,803 B2
• Filed: 09/25/2007
• Issued: 01/18/2011
• Est. Priority Date: 09/25/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Cheng, Steven S.
• Primary Examiner(s): Gu; Shawn X
• Application Number:
  US11/861,146
• Publication Number:
  US 20090083485A1
• Time in Patent Office: 1,211 Days
• Field of Search: None
• US Class Current: 711/161
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G11C 29/74 using duplex memories, i.e. using dual copies
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

A nonvolatile memory array includes two or more devices, each device containing data that is scrambled using a different scrambling scheme. When the same data is provided and stored in both devices, different data patterns occur in each device, so that if one of the patterns causes data pattern induced errors, the original data can be recreated from another copy that does not share the same data pattern.

Claims

1. A method of securely storing data in a nonvolatile memory array comprising:

transforming a portion of data according to a first transformation to obtain first transformed data;

storing the first transformed data in a first portion of the memory array;

transforming the portion of data according to a second transformation to obtain second transformed data;

storing the second transformed data in a second portion of the memory array while the first transformed data is stored in the first portion of the memory array, to provide redundant storage of the portion of data;

subsequently, in response to attempting to read the first transformed data from the first portion of the memory array and determining that the first transformed data is uncorrectable by error correction code, reading the second transformed data from the second portion of the memory array and

using the second transformed data to recover the portion of data and subsequently transforming the portion of data according to a third transformation to obtain third transformed data, storing the third transformed data in a third portion of the memory array and erasing the stored first transformed data.

2. The method of claim 1 wherein the first transformation scrambles data based on a first seed and the second transformation scrambles data based on a second seed.

3. The method of claim 1 wherein transforming the portion of data according to the first transformation is performed in parallel with transforming the portion of data according to the second transformation.

4. The method of claim 1 wherein the first portion of the memory array is a first block and the second portion of the memory array is a second block.

5. The method of claim 1 wherein the first portion of the memory array is a first plane and the second portion of the memory array is a second plane.

6. The method of claim 1 wherein the first portion of the memory array is a first die and the second portion of the memory array is a second die.

7. A nonvolatile memory system comprising:

a memory array;

a memory controller configured to perform the following operations;

transforming a portion of data according to a first transformation to obtain first transformed data

storing the first transformed data in a first portion of the memory array;

transforming the portion of data according to a second transformation to obtain second transformed data;

storing the second transformed data in a second portion of the memory array while the first transformed data is stored in the first portion of the memory array, to provide redundant storage of the portion of data

subsequently, in response to attempting to read the first transformed data from the first portion of the memory array and determining that the first transformed data is uncorrectable by error correction code, reading the second transformed data from the second portion of the memory array and

using the second transformed data to recover the portion of data and subsequently transforming the portion of data according to a third transformation to obtain third transformed data, storing the third transformed data in a third portion of the memory array and erasing the stored first transformed data.

8. The nonvolatile memory system of claim 7 wherein the memory controller further comprises a first scrambler unit that contains a first exclusive OR (XOR) circuit to perform XOR operations using a first number and a second scrambler that contains a second XOR circuit to perform XOR operations using a second number.

9. The nonvolatile memory system of claim 8 wherein the first scrambler unit and the second scrambler unit scramble the same data in parallel.

10. The nonvolatile memory system of claim 7 wherein the first memory array portion is a first block and the second memory array portion is a second block.

11. The nonvolatile memory system of claim 7 wherein the first memory array portion is a first plane and the second memory array portion is a second plane.

12. The nonvolatile memory system of claim 7 wherein the first memory array portion is a first die and the second memory array portion is a second die.

13. The nonvolatile memory system of claim 7 wherein the memory system is in a removable memory card.

14. The nonvolatile memory system of claim 7 where the first and second transformations are reversible transformations.