Partitioning a large design across multiple devices

• US 7,873,927 B1
• Filed: 04/03/2008
• Issued: 01/18/2011
• Est. Priority Date: 03/03/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Ranjan, Abhishek, Knol, David A., Raje, Salil Ravindra
• Primary Examiner(s): Levin; Naum B
• Application Number:
  US12/062,447
• Time in Patent Office: 1,020 Days
• Field of Search: 716 7- 11, 716 16- 18
• US Class Current: 716/124
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method of partitioning a design across a plurality of integrated circuits can include creating a software construct for each one of the plurality of integrated circuits and assigning a plurality of instances to a selected software construct. Each of the plurality of instances can be from a different logic hierarchy. The method further can include automatically adding at least one input/output buffer and port to the selected software construct to accommodate the plurality of instances and creating nets connecting the plurality of instances and the at least one input/output buffer and port within the selected software construct.

Claims

1. A method of segmenting a design across a plurality of integrated circuits (ICs), said method comprising:

creating, using a computer, a data structure representing a physical area of an IC of the plurality of ICs for each one of the plurality of ICs;

assigning at least a first instance from a logic hierarchy of the design to a first data structure corresponding to a first IC of the plurality of ICs;

assigning at least a second instance from the logic hierarchy of the design to a second data structure corresponding to a second IC of the plurality of ICs;

automatically adding at least one of an input/output buffer and port to the first and second data structures; and

creating nets connecting the plurality of instances and the input/output buffer and port within the first and second data structures.

2. The method of claim 1, further comprising determining connectivity between the first and second data structures.

3. The method of claim 1, further comprising indicating connectivity between the first and second data structures.

4. The method of claim 1, further comprising determining whether a number of connections between the first and second data structures exceeds a threshold determined, at least in part, from at least one of a number of inputs or outputs available on the first and second ICs associated with the first and second data structures.

5. The method of claim 4, further comprising providing an indication that the threshold was exceeded if the number of connections exceeds the threshold.

6. The method of claim 1, wherein the data structure is a pblock which corresponds to a physical area on the IC.