Strain-silicon CMOS using etch-stop layer and method of manufacture

• US 7,875,543 B1
• Filed: 08/28/2008
• Issued: 01/25/2011
• Est. Priority Date: 06/07/2005
• Status: Expired due to Fees

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Nayak, Deepak Kumar, Luo, Yuhao
• Primary Examiner(s): Nhu; David
• Application Number:
  US12/200,851
• Time in Patent Office: 880 Days
• Field of Search: 438/197, 438/270, 438/637, 438/597, 438/634, 438/635, 438/733, 438/740, 438/753, 257/E21.576, 257/663, 257/635
• US Class Current: 438/597
• CPC Class Codes: H01L 21/31105 Etching inorganic layers
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide strain in the plane of the channel region. In a particular embodiment, a tensile silicon nitride layer is formed over recesses of an NMOS transistor in a CMOS cell, and a compressive silicon nitride layer is formed over recesses of a PMOS transistor in the CMOS cell. In a particular embodiment the stressed silicon nitride layer(s) is a chemical etch stop layer.

Claims

1. A method of fabricating a transistor comprising:

forming sidewall spacers on a gate;

etching silicon in source and drain regions to form recesses below an original surface of the silicon;

forming an ohmic contact layer over the source and drain regions; and

forming a stressed silicon nitride layer in the recesses over at least portions of the ohmic contact layer proximate to the gate.

2. The method of fabricating a transistor according to claim 1 wherein the step of etching silicon comprises an anisotropic silicon etch.

3. The method of fabricating a transistor according to claim 1 wherein the step of forming the ohmic contact layer includes sub-steps of

depositing a layer of silicide-forming material, and

thermally treating the transistor to form a silicide layer.

4. The method of fabricating a transistor according to claim 1 wherein the sidewall spacers comprise an oxide having a thickness of between about 5 nanometers and about 200 nanometers.

5. The method of fabricating a transistor according to claim 1 wherein the recesses are etched to a depth of between about 5 nanometers and about 50 nanometers.

6. The method of fabricating a transistor according to claim 1 wherein the stressed silicon nitride layer forms a chemical etch stop layer.

7. The method of fabricating a transistor according to claim 1 wherein the transistor is portion of a complementary metal-oxide-semiconductor (“

CMOS”

) cell having a second transistor, and the stressed silicon nitride layer has a first stress type, and further comprising;

forming a second stressed silicon nitride layer having a second stress type over the second transistor.

8. The method of fabricating a transistor according to claim 7 wherein the stressed silicon nitride layer and the second stressed silicon nitride layer form a chemical etch stop layer.