Multi-regulator power delivery system for ASIC cores

• US 7,875,996 B2
• Filed: 12/21/2007
• Issued: 01/25/2011
• Est. Priority Date: 12/21/2007
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chi, Steve X., Nguyen, Daniel P., Lai, Po-Shen
• Primary Examiner(s): Fureman; Jared J
• Assistant Examiner(s): AMAYA, CARLOS DAVID
• Application Number:
  US12/005,144
• Publication Number:
  US 20090160421A1
• Time in Patent Office: 1,131 Days
• Field of Search: 307/80, 307/82, 307/85
• US Class Current: 307/80
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An electronic product includes an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product. Control logic of the ASIC device is responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation.

Claims

1. An electronic apparatus, comprising:

an application specific semiconductor chip (ASIC) device;

a linear regulator module configured to be optionally coupled in operation to an external-to-the ASIC device capacitor via a node;

a capless regulator module coupled to internal capacitance of the ASIC device via the node; and

control logic executable by the ASIC device, the control logic responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device.

2. The apparatus of claim 1, wherein the linear regulator module includes at least a first and a second linear regulator sub-module, the first linear regulator sub-module configured to provide up to a first level of electrical current and the second linear regulator sub-module configured to provide up to a second level of electrical current.

3. The apparatus of claim 2, wherein the second level of electrical current is greater than the first level of electrical current.

4. The apparatus of claim 1, wherein the regulator selection signal is communicated to the control logic with a regulator selection pin.

5. The apparatus of claim 4, wherein the regulator selection signal is permanently fixed to a particular voltage level.

6. The apparatus of claim 1, wherein the ASIC device is initially configured to use a default selection of one of the linear regulator module and the capless regulator module prior to the completion of initial power-up of at least a portion the ASIC device.

7. The apparatus of claim 6, wherein the linear regulator module includes at least a first and a second linear regulator sub-module, the first linear regulator sub-module configured to provide up to a first level of electrical current and the second linear regulator sub-module configured to provide up to a second level of electrical current.

8. The apparatus of claim 7, wherein the second level of electrical current is greater than the first level of electrical current.

9. The apparatus of claim 1, wherein the regulator selection signal is obtained from a pre-programmed configuration register accessible by the ASIC device.

10. An electronic apparatus, comprising:

an application specific semiconductor chip (ASIC) device;

a linear regulator module configured to be coupled in operation to an optional external capacitor via a node;

a capless regulator module coupled to internal capacitance of the ASIC device via the node; and

control logic executable by the ASIC device, the control logic responsive to a stored state of a configuration register accessible by the ASIC device for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device.

11. The apparatus of claim 10, wherein the linear regulator module includes at least a first and a second linear regulator sub-module, the first linear regulator sub-module configured to provide up to a first level of electrical current and the second linear regulator sub-module configured to provide up to a second level of electrical current.

12. The apparatus of claim 11, wherein the second level of electrical current is greater than the first level of electrical current.

13. The apparatus of claim 10, wherein the regulator selection signal is communicated to the control logic with a regulator selection pin.

14. The apparatus of claim 13, wherein the regulator selection signal is permanently fixed to a particular voltage level.

15. The apparatus of claim 10, wherein the ASIC device is initially configured to use a predetermined one of the linear regulator module and the capless regulator module prior to the completion of initial power-up of at least a portion the ASIC device.

16. The apparatus of claim 15, wherein the linear regulator module includes at least a first and a second linear regulator sub-module, the first linear regulator sub-module configured to provide up to a first level of electrical current and the second linear regulator sub-module configured to provide up to a second level of electrical current.

17. The apparatus of claim 16, wherein the second level of electrical current is greater than the first level of electrical current.

18. The apparatus of claim 10, wherein the regulator selection signal is obtained from a pre-programmed configuration register accessible by the ASIC device.

19. A memory device, comprising:

a memory array;

an interface circuit configured to communicate with a host device;

a controller coupled to communicate with the memory array and with the interface circuit, the controller implemented on an ASIC device, the controller including;

a linear regulator module configured to be optionally coupled in operation to an external-to-the-ASIC device capacitor via a node;

a capless regulator module coupled to an internal capacitance of the ASIC device via the node; and

control logic executable by the ASIC device, the control logic responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device.

20. The memory device of claim 19, wherein the linear regulator module includes at least a first and a second linear regulator sub-module, the first linear regulator sub-module configured to provide up to a first level of electrical current and the second linear regulator sub-module configured to provide up to a second level of electrical current.

21. The apparatus of claim 20, wherein the second level of electrical current is greater than the first level of electrical current.

22. The apparatus of claim 19, wherein the regulator selection signal is communicated to the control logic with a regulator selection pin.

23. The apparatus of claim 22, wherein the regulator selection signal is permanently fixed to a particular voltage level.

24. The apparatus of claim 19, wherein the ASIC device is initially configured to use a default selection of one of the linear regulator module and the capless regulator module prior to the completion of initial power-up of at least a portion the ASIC device.

25. The apparatus of claim 24, wherein the linear regulator module includes at least a first and a second linear regulator sub-module, the first linear regulator sub-module configured to provide up to a first level of electrical current and the second linear regulator sub-module configured to provide up to a second level of electrical current.

26. The apparatus of claim 25, wherein the second level of electrical current is greater than the first level of electrical current.

27. The apparatus of claim 19, wherein the regulator selection signal is obtained from a pre-programmed configuration register accessible by the ASIC device.

28. A method for operating an electronic apparatus, the apparatus including an ASIC device, a linear regulator module configured to be optionally coupled to an external-to-the-ASIC device capacitor via a node and a capless regulator module coupled to an internal capacitance of the ASIC device via the node, the method comprising:

applying power to the ASIC device to initiate power-up of the ASIC device;

selecting one of the linear regulator module and the capless regulator module to provide power to the ASIC device during power-up of the ASIC device;

completing the power-up of the ASIC device; and

choosing one of the linear regulator and the capless regulator module to provide power to the ASIC device after power-up of the ASIC device.

29. The method of claim 28, wherein the selecting is achieved by executing control logic in the ASIC device.

30. The method of claim 28, wherein the selecting is achieved by using a predetermined one of the linear regulator module and the capless regulator module in response to a regulator selection signal.

31. The method of claim 30, wherein the regulator selection signal is permanently fixed to a particular voltage.

32. The method of claim 30, wherein the regulator selection signal is responsive to a stored state of a configuration register accessible by the ASIC device.

33. The method of claim 28, wherein the selecting is responsive to a state of a pin coupled to the ASIC device.

34. The method of claim 28, wherein the choosing is achieved by executing control logic in the ASIC device.

35. The method of claim 34, wherein the choosing is responsive to a stored state of a configuration register accessible by the ASIC device.

36. The method of claim 34, wherein the choosing is responsive to a state of a pin coupled to the ASIC device.

37. A method for powering up an ASIC device of an electronic apparatus, the ASIC device including a linear regulator module configured to be optionally coupled in operation to an external-to-the ASIC device capacitor via a node and a capless regulator module coupled to an internal capacitance of the electronic product via the node, the method comprising:

initiating power-up of the ASIC device;

selecting one of the linear regulator module and the capless regulator module for powering the ASIC device during power-up of the ASIC device;

completing the power-up of the ASIC device; and

choosing one of the linear regulator module and the capless regulator module for powering the ASIC device after power-up of the ASIC device.

38. The method of claim 37, wherein the capless regulator module includes at least a first and a second capless regulator sub-module, the first capless regulator sub-module configured to provide up to a first level of electrical current and the second capless regulator sub-module configured to provide up to a second level of electrical current, and in cases where the capless regulator module is selected, the selecting further comprises:

selecting the first capless regulator sub-module of the capless regulator module for powering the ASIC device during power-up.

39. The method of claim 38, wherein the first level of electrical current is less than the second level of electrical current.

40. The method of claim 37, wherein the linear regulator module includes at least a first and a second linear regulator sub-module, the first linear regulator sub-module configured to provide up to a first level of electrical current and the second linear regulator sub-module configured to provide up to a second level of electrical current, and wherein in cases where the linear regulator module is chosen, the choosing further comprises:

choosing the first linear regulator sub-module of the linear regulator module for powering the ASIC device during power-up.

41. The method of claim 40, wherein the first level of electrical current is less than the second level of electrical current.

42. A method for operating a memory device, the memory device including a memory array, an interface circuit configured to communicate with a host device, a controller coupled to communicate with the memory array and the interface circuit, the controller implemented on an ASIC device, the controller including a linear regulator module configured to be optionally coupled in operation to an external-to-the ASIC device capacitor via a node, a capless regulator module coupled to an internal capacitance of the ASIC device via the node;

and control logic executable by the ASIC device, the control logic responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device, the method comprising;

applying power to the ASIC device to initiate power-up of the ASIC device;

selecting one of the linear regulator module and the capless regulator module to provide power to the ASIC device during power-up of the ASIC device;

completing the power-up of the ASIC device; and

choosing one of the linear regulator and the capless regulator module to provide power to the ASIC device after power-up of the ASIC device.

43. The method of claim 42, wherein the linear regulator module includes at least a first and a second linear regulator sub-module, the first linear regulator sub-module is configured to provide up to a first level of electrical current and the second linear regulator sub-module is configured to provide up to a second level of electrical current.

44. The method of claim 42, wherein the selecting is achieved by executing control logic in the ASIC device.

45. The method of claim 44, wherein the regulator selection signal is responsive to a stored state of a configuration register accessible by the ASIC device.

46. The method of claim 42, wherein the selecting is achieved by using a predetermined one of the linear regulator module and the capless regulator module in response to a regulator selection signal.

47. The method of claim 44, wherein the regulator selection signal is permanently fixed to a particular voltage.

48. The method of claim 42, wherein the selecting is responsive to a state of a pin coupled to the ASIC device.

49. The method of claim 48, wherein the choosing is responsive to a state of a pin coupled to the ASIC device.

50. The method of claim 42, wherein the choosing is achieved by executing control logic in the ASIC device.

51. The method of claim 48, wherein the choosing is responsive to a stored state of a configuration register accessible by the ASIC device.