Integrated battery voltage sensor with high voltage isolation, a battery voltage sensing system and methods therefor

• US 7,876,071 B2
• Filed: 06/15/2007
• Issued: 01/25/2011
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies ECBU IP Singapore Pte Limited (Broadcom, Inc.)
• Inventors: Zhang, Bin, Lum, Kok Keong Richard, Chow, Fun Kok, Chen, Lei
• Primary Examiner(s): Tso; Edward
• Assistant Examiner(s): Fantu; Yalkew
• Application Number:
  US11/763,522
• Publication Number:
  US 20080309317A1
• Time in Patent Office: 1,320 Days
• Field of Search: 320/135, 320/136, 324/433
• US Class Current: 320/136
• CPC Class Codes: G01R 19/0084 measuring voltage only all subgroups of G01R19/00 take precedence
• CPC Class Codes: H01M 10/425 Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing printed circuits H05K1/00
• CPC Class Codes: H01M 10/48 Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

An integrated circuit battery sensor and system thereof are provided. The battery sensor includes a voltage sensor configured to sample a voyage of a battery and a buffer in electrical communication with the voltage sensor and configured for scaling the sampled battery voltage and outputting a voltage signal proportional to the sampled battery voltage; wherein the voltage sensor is further configured for isolating the buffer from the battery. The voltage sensor includes a first capacitor coupled to a positive potential terminal of the battery and a second capacitor coupled to a negative potential terminal of the battery. The battery sensor includes a first die including a first and second input terminal configured for coupling to the positive and negative potential terminals of the battery; and a second die including the voltage sensor, wherein the first and second die are electrically isolated from each other.

Claims

1. An integrated circuit for sensing a voltage of at least one battery, comprising:

(a) a first circuit comprising a first switching device, a receiver and first and second input terminals configured to be operatively coupled to a positive terminal and a negative terminal of the battery, respectively, by the first switching device;

(b) a second circuit comprising a buffer configured to provide an output voltage signal representative of the sampled battery voltage, a sample and hold signal generator, and a digital driver, and

(c) an isolation barrier disposed between the first circuit and the second circuit and comprising first, second, third and fourth capacitors;

wherein the first input terminal is switchably coupled to the first capacitor through the first switching device and the second input terminal is coupled to the second capacitor, the first switching device is configured to couple the first circuit to the first and second input terminals during a sample phase to sense the voltage of the battery and to couple the first circuit to the buffer during a hold phase, the second circuit is configured to receive the sensed voltage from the first and second capacitors during the hold phase and present a scaled version of the sensed voltage to the buffer, the sample and hold generator is operatively coupled to the buffer, the timing and operation of the buffer with respect to receiving the scaled version of the sensed voltage during the hold phase is controlled by the sample and hold signal generator, the sample and hold signal generator is further configured to provide at least a first sample and hold signal through the digital driver, the third and fourth capacitors, and the receiver to the first switch to control the timing of the operation of the first switch with respect to the sample phase and the hold phase, the sample and hold generator is further configured to receive an enable signal from an external source, the enable signal being translated by the sample and hold generator into the first sample and hold signal.

2. The integrated circuit of claim 1, wherein the buffer is a zero order sample and hold circuit.

3. The integrated circuit of claim 1, wherein the buffer is a sample and hold circuit with a first-order low pass filter characteristic.

4. The integrated circuit of claim 1, further comprising a first continuous-time filter coupled to the output of the buffer.

5. The integrated circuit of claim 4, further comprising a second filter coupled to an output of the first filter configured for outputting a desired frequency response of the output voltage signal.

6. The integrated circuit of claim 1, further comprising a cell balancing circuit configured for diverting current from the battery.

7. The integrated circuit of claim 6, wherein the sample and hold generator is further configured to provide a current divert signal to control the cell balancing circuit.

8. The integrated circuit of claim 7, further comprising a decoder coupled between the first capacitor and the cell balancing circuit, the decoder being configured to decode the current divert signal from the first signal.

9. The integrated circuit of claim 1, wherein the first circuit is disposed on a first die.

10. The integrated circuit of claim 9, wherein the second circuit is disposed on a second die.

11. The integrated circuit of claim 10, wherein the first and second dice are electrically isolated from one other by the isolation barrier.

12. The integrated circuit of claim 1, wherein an analog-to-digital converter is coupled to the output of the buffer and is configured to output a digital representation of the sampled voltage therefrom.

13. The integrated circuit of claim 12, further comprising a controller configured to receive the digital representation of the sampled voltage and to generate the enable signal.