High speed multiple memory interface I/O cell

• US 7,876,123 B2
• Filed: 04/25/2008
• Issued: 01/25/2011
• Est. Priority Date: 10/09/2007
• Status: Active Grant

• Current Assignee: Broadcom International Pte Ltd. (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Lim, Hong-Him, Bhakta, Dharmesh, Randazzo, Todd, Kong, Cheng-Gang
• Primary Examiner(s): Barnie; Rexford N
• Assistant Examiner(s): RICHARDSON, JANY
• Application Number:
  US12/109,497
• Publication Number:
  US 20090091349A1
• Time in Patent Office: 1,005 Days
• Field of Search: 326/62, 326 82- 83, 326 86- 87, 327/108, 327/109
• US Class Current: 326/30
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements

Abstract

An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

Claims

1. An input/output (I/O) cell comprising:

a predriver circuit configured to generate a first driver control signal and a second driver control signal in response to a drive control signal, a on-die termination control signal, a slew control signal, and a data output signal, wherein said predriver circuit comprises a binary programmable predriver comprising (i) a plurality of first drivers, each first driver comprising a programmable binary weighted cascode ngate driver, and (ii) a plurality of second drivers, each second driver comprising a programmable binary weighted cascode pgate driver;

an output driver circuit comprising (i) a plurality of driver-capable segments configured to provide a binary weighted drive network and (ii) a plurality of on-die termination (ODT) capable segments configured to provide a binary weighted termination network, wherein said output driver circuit is configured (i) to drive an input/output pad in a first mode and (ii) provide on-die termination of said input/output pad in a second mode in response to said first driver control signal and said second driver control signal.

2. The input/output cell according to claim 1, wherein said input/output cell is configurable to meet drive impedance ranges, ODT impedance ranges, I/O voltage ranges and slew rate ranges for any of a plurality of memory interface specifications in response to (i) a drive control signal, (ii) a on-die termination control signal and (iii) a slew control signal.

3. The input/output cell according to claim 1, further comprising a receiver circuit configured to receive an input signal from said input/output pad and compare a voltage level of said input signal with a predetermined reference voltage.

4. The input/output cell according to claim 1, further comprising a control circuit configured to interface said input/output cell with an integrated circuit core and generate (i) said drive control signal, (ii) said on-die termination control signal, (iii) said slew control signal and (iv) said data signal.

5. The input/output cell according to claim 1, further comprising:

a control circuit configured (i) to generate said drive control signal, said on-die termination control signal, said slew control signal, and said data output signal and (ii) to receive a data input signal;

and

a receiver circuit configured to receive an input signal from said input/output pad, compare a voltage level of said input signal with a predetermined reference voltage, and present a data input signal to said control circuit.

6. The input/output cell according to claim 5, wherein said control circuit comprises a core interface circuit.

7. The input/output cell according to claim 1, wherein said binary programmable predriver circuit further comprises:

and

an on-die termination (ODT) sequencer.

8. The input/output cell according to claim 7, wherein said ODT sequencer provides dynamic switching between an input/output mode and a termination mode.

9. The input/output cell according to claim 7, wherein said on-die termination (ODT) sequencer comprises a dynamic on-die termination sequencer comprising:

a first circuit configured to generate a on-die termination mode control signal in response to an enable signal, a termination control signal and a data signal; and

a second circuit configured to generate a driver mode control signal in response to the enable signal, the termination control signal and the data signal.

10. The input/output cell according to claim 1, wherein said programmable binary weighted cascode ngate driver comprises a programmable 5-bit binary weighted cascode driver and each of said plurality of first drivers further comprises:

a multiplexer circuit; and

a NAND data path.

11. The input/output cell according to claim 1, wherein said programmable binary weighted cascode pgate driver comprises a programmable 5-bit binary weighted cascode driver and each of said plurality of second drivers further comprises:

a multiplexer circuit; and

a NOR data path.

12. The input/output cell according to claim 1, wherein each of said plurality of driver-capable segments comprises a first transistor, a second transistor, a first resistor, a second resistor a third resistor, and a fourth resistor, a source of the first transistor receives an I/O supply voltage, a gate of the first transistor receives said first driver control signal, a drain of the first transistor is connected to a first terminal of the first resistor and a first terminal of the second resistor, a second terminal of the first resistor, a second terminal of the second resistor, a first terminal of the third resistor and a first terminal of the fourth resistor are connected together, a second terminal of the third resistor and a second terminal of the fourth resistor are connected to a drain of the second transistor, a gate of the second transistor receives said second driver control signal, and a source of the second transistor is connected to an I/O power supply ground potential.

13. The input/output cell according to claim 12, wherein the resistors comprise oxide-isolated poly resistors.

14. The input/output cell according to claim 1, wherein at least one of said plurality of ODT-capable segments comprises a first transistor, a second transistor, a first resistor, a second resistor a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor, a source of the first transistor receives an I/O supply voltage, a gate of the first transistor receives said first driver control signal, a drain of the first transistor is connected to a first terminal of the first resistor and a first terminal of the second resistor, a second terminal of the first resistor is connected to a first terminal of the third resistor, a second terminal of the second resistor is connected to a first terminal of the fourth resistor, a second terminal of the third resistor, a second terminal of the fourth resistor, a first terminal of the fifth resistor and a first terminal of the sixth resistor are connected together, a second terminal of the fifth resistor is connected to a first terminal of the seventh resistor, a second terminal of the sixth resistor is connected to a first terminal of the eighth resistor, a second terminal of the seventh resistor and a second terminal of the eighth resistor are connected to a drain of the second transistor, a gate of the second transistor receives said second driver control signal, and a source of the second transistor is connected to an I/O power supply ground potential.

15. The input/output cell according to claim 14, wherein the resistors comprise oxide-isolated poly resistors.

16. The input/output cell according to claim 1, wherein at least one of said plurality of ODT-capable segments comprises a first tied-off field effect transistor and two series resistors configured as a pull-up and a second tied-off field effect transistor and two series resistors configured as a pull-down.

17. The input/output cell according to claim 1, wherein at least one of said plurality of ODT-capable segments comprises two series field effect transistors and four series resistors configured as a pull-up and two series field effect transistors and four series resistors configured as a pull-down.

18. The input/output cell according to claim 1, wherein at least one of said plurality of ODT-capable segments comprises four series field effect transistors and eight series resistors configured as a pull-up and four series field effect transistors and eight series resistors configured as a pull-down.

19. An input/output (I/O) cell comprising:

a plurality of driver-capable segments configured to provide a binary weighted drive network; and

a plurality of on-die termination (ODT) capable segments configured to provide a binary weighted termination network, wherein said I/O cell is configured to drive an input/output pad in a first mode and provide on-die termination of said input/output pad in a second mode, and wherein each of said plurality of driver-capable segments comprises a first transistor, a second transistor, a first resistor, a second resistor a third resistor, and a fourth resistor, a source of the first transistor receives an I/O supply voltage, a gate of the first transistor receives said first driver control signal, a drain of the first transistor is connected to a first terminal of the first resistor and a first terminal of the second resistor, a second terminal of the first resistor, a second terminal of the second resistor, a first terminal of the third resistor and a first terminal of the fourth resistor are connected together, a second terminal of the third resistor and a second terminal of the fourth resistor are connected to a drain of the second transistor, a gate of the second transistor receives said second driver control signal, and a source of the second transistor is connected to an I/O power supply ground potential.

20. An input/output (I/O) cell comprising:

a plurality of driver-capable segments configured to provide a binary weighted drive network; and

a plurality of on-die termination (ODT) capable segments configured to provide a binary weighted termination network, wherein said I/O cell is configured to drive an input/output pad in a first mode and provide on-die termination of said input/output pad in a second mode, and wherein at least one of said plurality of ODT-capable segments comprises a first transistor, a second transistor, a first resistor, a second resistor a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor, a source of the first transistor receives an I/O supply voltage, a gate of the first transistor receives said first driver control signal, a drain of the first transistor is connected to a first terminal of the first resistor and a first terminal of the second resistor, a second terminal of the first resistor is connected to a first terminal of the third resistor, a second terminal of the second resistor is connected to a first terminal of the fourth resistor, a second terminal of the third resistor, a second terminal of the fourth resistor, a first terminal of the fifth resistor and a first terminal of the sixth resistor are connected together, a second terminal of the fifth resistor is connected to a first terminal of the seventh resistor, a second terminal of the sixth resistor is connected to a first terminal of the eighth resistor, a second terminal of the seventh resistor and a second terminal of the eighth resistor are connected to a drain of the second transistor, a gate of the second transistor receives said second driver control signal, and a source of the second transistor is connected to an I/O power supply ground potential.

21. An input/output (I/O) cell comprising:

a plurality of driver-capable segments configured to provide a binary weighted drive network; and

a plurality of on-die termination (ODT) capable segments configured to provide a binary weighted termination network, wherein said I/O cell is configured to drive an input/output pad in a first mode and provide on-die termination of said input/output pad in a second mode, and wherein at least one of said plurality of ODT-capable segments comprises two series field effect transistors and four series resistors configured as a pull-up and two series field effect transistors and four series resistors configured as a pull-down.

22. An input/output (I/O) cell comprising:

a plurality of driver-capable segments configured to provide a binary weighted drive network; and

a plurality of on-die termination (ODT) capable segments configured to provide a binary weighted termination network, wherein said I/O cell is configured to drive an input/output pad in a first mode and provide on-die termination of said input/output pad in a second mode, and wherein at least one of said plurality of ODT-capable segments comprises four series field effect transistors and eight series resistors configured as a pull-up and four series field effect transistors and eight series resistors configured as a pull-down.