Drive device

• US 7,876,291 B2
• Filed: 02/27/2006
• Issued: 01/25/2011
• Est. Priority Date: 03/30/2005
• Status: Expired due to Fees

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Systems Company Limited
• Inventors: Tada, Gen, Shigeta, Yoshihiro, Kobayashi, Hideto, Shimabukuro, Hiroshi
• Primary Examiner(s): Lefkowitz; Sumati
• Assistant Examiner(s): Moon; Seokyun
• Application Number:
  US11/362,517
• Publication Number:
  US 20060223254A1
• Time in Patent Office: 1,793 Days
• Field of Search: 345/211, 345/212, 345 60- 72, 3151691-1694
• US Class Current: 345/63
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/293 for address discharge
• CPC Class Codes: G09G 3/296 Driving circuits for producing the waveforms applied to the driving electrodes

Abstract

A display panel drive device of reduced area occupied by circuit elements. The display panel drive device includes an output stage circuit having a low side selector circuit constituted by connecting in series inverters and a buffer circuit, n-channel IGBTs, a Zener diode and resistance respectively connected between the gate and emitter of the IGBT, a buffer circuit, and a high side selector circuit including an inverter. The buffer circuit includes a high side Pch-MOS operated by a logic signal from the high side selector circuit and a low side Nch-MOS operated by a logic signal of the low side selector circuit.

Claims

1. A drive device for driving a display panel, comprising:

an output stage circuit, including an output circuit connected with a scanning electrode of the display panel, and

a drive circuit including a selector and shift register for controlling the output circuit,

wherein the output stage circuit is driven by a high side logic voltage and a low side logic voltage, the high side logic voltage has an amplitude between a high power source voltage and a high ground voltage, the low side logic voltage has an amplitude between a low power source voltage and a low ground voltage, and the high power source voltage and the high ground voltage are higher than the low power source voltage and the low ground voltage, respectively,

wherein the drive circuit includes a first drive circuit for low side use and a second drive circuit for high side use, which respectively control the low side and high side of the output circuit, the first drive circuit for low side use being driven by the low side logic voltage and the second drive circuit for high side use being driven by the high side logic voltage,

wherein one of the first and second drive circuits includes a level shifter circuit for sharing one of a high side logic signal and a low side logic signal,

wherein the level shifter circuit is constituted by first, second, third and fourth P-channel MOSFETs, and first and second N-channel MOSFETs, the source and substrate of the first and second P-channel MOSFETs are respectively connected with the high side power source, the drain outputs of the first and second P-channel MOSFETs are respectively connected with the source and substrate of the third and fourth P-channel MOSFETs, and the drain outputs of the third and fourth P-channel MOSFETs are respectively connected with the source and substrate of the first and second N-channel MOSFETs.

2. The display panel drive device according to claim 1, wherein the first and second drive circuits are driven by logic voltages of respectively equal magnitudes.

3. The display panel drive device according to claim 1, wherein the first and second drive circuits are integrated circuits driven by logic voltages of 0 V to 5 V.

4. The display panel drive device according to claim 1, wherein the level shifter circuit is constituted by a plurality of P-channel and N-channel MOSFETs gate-controlled by the logic voltages.

5. The display panel drive device according to claim 1, further comprising in the level shifter circuit,

a first Zener diode between the high side power source and the high side ground potential and

second and third Zener diodes respectively between the drain and source of the first and second P-channel MOSFETs whose substrate and source are connected with the high side power source.

6. A drive device for driving a display panel, comprising:

an output stage circuit, including an output circuit connected with a scanning electrode of the display panel, and

a drive circuit for controlling the output circuit,

wherein the output stage circuit is driven by a low side logic voltage and a high side logic voltage, the high side logic voltage has an amplitude between a high power source voltage and a high ground voltage, the low side logic voltage has an amplitude between a low power source voltage and a low ground voltage, and the high power source voltage and the high ground voltage are higher than the low power source voltage and the low ground voltage, respectively;

the drive circuit includes a first drive circuit including a selector and shift register for controlling the output circuit and a second drive circuit including a selector for controlling the output circuit, which respectively control the low side and high side of the output circuit, the first drive circuit being driven by the low side logic voltage and the second drive circuit being driven by the high side logic voltage;

one of the first and second drive circuits includes a level shifter circuit for sharing one of a high side logic signal and a low side logic signal; and

the level shifter circuit alternately turns the high side logic signal ON and OFF at each odd bit or even bit, in synchronization with a clock signal for the first drive circuit.

7. A drive device comprising:

an output circuit and

a drive circuit including a selector and shift register for controlling the output circuit,

wherein the output stage circuit is driven by a high side logic voltage and a low side logic voltage, the high side logic voltage has an amplitude between a high power source voltage and a high ground voltage, the low side logic voltage has an amplitude between a low power source voltage and a low ground voltage, and the high power source voltage and the high ground voltage are higher than the low power source voltage and the low ground voltage, respectively,

wherein the drive circuit includes a first drive circuit for low side use and a second drive circuit for high side use, which respectively control the low side and high side of the output circuit, the first drive circuit for low side use being driven by the low side logic voltage and the second drive circuit for high side use being driven by the high side logic voltage,

wherein one of the first and second drive circuits includes a level shifter circuit for sharing one of a high side logic signal and a low side logic signal,

wherein the level shifter circuit is constituted by first, second, third and fourth P-channel MOSFETs, and first and second N-channel MOSFETs, the source and substrate of the first and second P-channel MOSFETs are respectively connected with the high side power source, the drain outputs of the first and second P-channel MOSFETs are respectively connected with the source and substrate of the third and fourth P-channel MOSFETs, and the drain outputs of the third and fourth P-channel MOSFETs are respectively connected with the source and substrate of the first and second N-channel MOSFETs.

8. The drive device according to claim 7, wherein the first and second drive circuits are driven by logic voltages of respectively equal magnitudes.

9. The drive device according to claim 7, wherein the first and second drive circuits are integrated circuits driven by logic voltages of 0 V to 5 V.

10. The drive device according to claim 7, wherein the level shifter circuit is constituted by a plurality of P-channel and N-channel MOSFETs gate-controlled by the logic voltages.

11. The drive device according to claim 7, further comprising in the level shifter circuit,

a first Zener diode between the high side power source and the high side ground potential and

second and third Zener diodes respectively between the drain and source of the first and second P-channel MOSFETs whose substrate and source are connected with the high side power source.

12. A drive device comprising:

an output circuit and

a drive circuit for controlling the output circuit,

wherein the output stage circuit is driven by a low side logic voltage and a high side logic voltage, the high side logic voltage has an amplitude between a high power source voltage and a high ground voltage, the low side logic voltage has an amplitude between a low power source voltage and a low ground voltage, and the high power source voltage and the high ground voltage are higher than the low power source voltage and the low ground voltage, respectively;

the drive circuit includes a first drive circuit including a selector and shift register for controlling the output circuit and a second drive circuit including a selector for controlling the output circuit, which respectively control the low side and high side of the output circuit, the first drive circuit being driven by the low side logic voltage and the second drive circuit being driven by the high side logic voltage;

one of the first and second drive circuits includes a level shifter circuit for sharing one of a high side logic signal and a low side logic signal of; and

the level shifter circuit alternately turns the high side logic signal ON and OFF at each odd bit or even bit, in synchronization with a clock signal for the first drive circuit.

13. A drive device for driving a display panel, comprising:

an output stage circuit, including

an output circuit having a high side n-channel transistor and a low side n-channel transistor connected to each other in series, and

a drive circuit including a selector and shift register for controlling the output circuit,

wherein the output stage circuit is driven by a high side logic voltage and a low side logic voltage, the high side logic voltage has an amplitude between a high power source voltage and a high ground voltage, the low side logic voltage has an amplitude between a low power source voltage and a low ground voltage, and the high power source voltage and the high ground voltage are higher than the low power source voltage and the low ground voltage, respectively,

wherein the drive circuit includes a first drive circuit including a low side selector and shift register for low side use and a second drive circuit including a high side selector and shift register for high side use, which respectively control the low side and high side of the output circuit, the first drive circuit for low side use being driven by the low side logic voltage and the second drive circuit for high side use being driven by the high side logic voltage, and

wherein the output stage circuit further includes a p-channel MOSFET in which a gate thereof is connected to an output of the high side selector, a drain thereof is connected to a gate of the high side n-channel transistor, and a source thereof is connected to the high power source voltage.