System and method for supporting standard and voltage optimized DIMMs

• US 7,876,592 B2
• Filed: 12/03/2008
• Issued: 01/25/2011
• Est. Priority Date: 12/03/2008
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Berke, Stuart A.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US12/327,292
• Publication Number:
  US 20100135097A1
• Time in Patent Office: 783 Days
• Field of Search: 365/51, 365/189.05
• US Class Current: 365/51
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A device includes a dynamic random access memory and a voltage regulator. The dynamic random access memory has a first input terminal connected to a first plurality of dual in-line memory module voltage pins, and a second input terminal. The dynamic random access memory is configured to receive a first voltage on the first input terminal. The voltage regulator has an input terminal connected to a second plurality of dual in-line memory module voltage pins, and an output terminal connected to the second input terminal of the dynamic random access memory. The voltage regulator is adapted to receive a second voltage, and configured to provide a third voltage to the second input terminal of the dynamic random access memory.

Claims

1. A system comprising:

a system board including;

a setup module configured to output an optimized signal if each of a plurality of dual in-line memory modules connected to a system board are voltage optimized dual in-line memory modules, and configured to output a standard signal if each of the plurality of dual in-line memory modules connected to the system board are standard dual in-line memory modules;

a first voltage regulator in communication with a first plurality of dual in-line memory module voltage pins, the first voltage regulator configured to output a first voltage to the first plurality of dual in-line memory module voltage pins in response to receiving the optimized signal, and further configured to output the first voltage to the first plurality of dual in-line memory module voltage pins in response to receiving the standard signal; and

an isolation switch in communication with a second plurality of dual in-line memory module voltage pins, the isolation switch configured to output a second voltage to the second plurality of dual in-line memory module voltage pins in response to receiving the optimized signal; and

a dual in-line memory module connected to the system board, the dual in-line memory module including;

a dynamic random access memory having a first input terminal connected to the first plurality of dual in-line memory module voltage pins, and a second input terminal, the dynamic random access memory configured to receive the first voltage on the first input terminal; and

a second voltage regulator having an input terminal connected to the second plurality of dual in-line memory module voltage pins, and an output terminal connected to the second input terminal of the dynamic random access memory, the second voltage regulator adapted to receive the second voltage, and configured to provide a third voltage to the second input terminal of the dynamic random access memory.

2. The system of claim 1 wherein the isolation switch is further configured to output the first voltage to the second plurality of dual in-line memory module voltage pins in response to receiving the standard signal.

3. The system of claim 1 wherein the first voltage is larger than the second voltage.

4. The system of claim 1 wherein the setup module is further configured to output a configuration error message in response to determining that a first portion of the plurality of dual in-line memory modules is voltage optimized dual in-line memory module, and a second portion of the plurality of dual in-line memory modules is standard dual in-line memory modules.

5. The system of claim 1 wherein the first plurality of dual in-line memory module voltage pins is greater than the second plurality of dual in-line memory module voltage pins.

6. The system of claim 1 wherein the dual in-line memory module further comprises:

a data buffer configured to receive the first voltage from via one of the second plurality of dual in-line memory module voltage pins, and further configured to receive the third voltage from the voltage regulator.

7. The system of claim 1 wherein an internal voltage regulator of the dynamic random access memory is bypassed.

8. A device comprising:

a dynamic random access memory having a first input terminal connected to a first plurality of dual in-line memory module voltage pins, and a second input terminal, the dynamic random access memory configured to receive a first voltage on the first input terminal; and

a voltage regulator having an input terminal connected to a second plurality of dual in-line memory module voltage pins, and an output terminal connected to the second input terminal of the dynamic random access memory, the voltage regulator adapted to receive a second voltage, and configured to provide a third voltage to the second input terminal of the dynamic random access memory, wherein a first portion of the dynamic random access memory is configured to operate at the first voltage, and a second portion of the dynamic random access memory is configured to operate at the third voltage.

9. The device of claim 8 wherein the voltage regulator is further configured to provide a fourth voltage to the dynamic random access memory.

10. The device of claim 9 wherein a first portion of the dynamic random access memory is configured to operate at the third voltage, and a second portion of the dynamic random access memory is configured to operate at the fourth voltage.

11. The device of claim 8 further comprising:

a data buffer configured to receive the first voltage from via one of the plurality of dual in-line memory module voltage pins, and further configured to receive the third voltage from the voltage regulator.

12. The device of claim 11 wherein the data buffer is further configured to receive a fourth voltage from the voltage regulator.

13. The device of claim 12 wherein a first portion of the data buffer is configured to operate at the first voltage, a second portion of the data buffer is configured to operate at the third voltage, and a third portion of the data buffer is configured to operate at the fourth voltage.

14. A method comprising:

receiving a serial presence detect for each of a plurality of dual in-line memory modules connected to a system board;

determining a dual in-line memory module type for each of the plurality of dual in-line memory modules based on the serial presence detect;

if each of the plurality of dual in-line memory modules are voltage optimized dual in-line memory modules, activating an isolation switch in response to determining that each of the plurality of dual in-line memory modules are voltage optimized dual in-line memory modules;

providing a first voltage to a first plurality of dual in-line memory module voltage pins, and a second voltage to a second plurality of dual in-line memory module voltage pins in response to activating the isolation switch;

receiving the first voltage at a dynamic random access memory;

receiving the second voltage at a voltage regulator; and

providing a third voltage from the voltage regulator to the dynamic random access memory.

15. The method of claim 14 further comprising:

providing a fourth voltage from the voltage regulator to the dynamic random access memory.

16. The method of claim 14 further comprising:

if each of the plurality of dual in-line memory modules are standard dual in-line memory modules, providing the first voltage to the first and second plurality of dual in-line memory module voltage pins.

17. The method of claim 14 further comprising:

providing the third voltage from the voltage regulator to a data buffer.

18. The method of claim 14 further comprising:

if a first portion of the plurality of dual in-line memory modules are voltage optimized and a second portion of the plurality of dual in-line memory modules are standard dual in-line memory modules, outputting a configured error signal.