Compensating for coupling during read operations in non-volatile storage

• US 7,876,611 B2
• Filed: 08/08/2008
• Issued: 01/25/2011
• Est. Priority Date: 08/08/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Ishigaki, Toru, Dong, Yingda, Dutta, Deepanshu, Chin, Henry, Lutze, Jeffrey W.
• Primary Examiner(s): Nguyen; Dang T
• Application Number:
  US12/188,629
• Publication Number:
  US 20100034022A1
• Time in Patent Office: 900 Days
• Field of Search: 365/185.02, 365/185.2, 365/238.5, 365/185.11, 365/185.18, 365/189.05, 365/185.03, 365/185.25, 365/185.22
• US Class Current: 365/185.02
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.

Claims

1. A method for operating non-volatile storage, comprising:

reading at least one bit line-adjacent storage element of a selected storage element to ascertain a data state of the at least one bit line-adjacent storage element, the at least one bit line-adjacent storage element and the selected storage element are associated with respective different adjacent bit lines; and

reading the selected storage element to ascertain a data state of the selected storage element, including applying different control gate read voltages, one at a time, to the selected storage element while setting voltages of the respective bit line of the at least one bit line-adjacent storage element based on its ascertained data state and the control gate read voltages.

2. The method of claim 1, wherein:

for each control gate read voltage, the voltage of the respective bit line of the at least one bit line-adjacent storage element is set according to a difference between the ascertained data state and a data state associated with the control gate read voltage, such that the voltage of the respective bit line of the at least one bit line-adjacent storage element is higher when the difference is greater.

3. The method of claim 1, wherein:

the reading at least one bit line-adjacent storage element occurs as part of a first step of a multi-step read operation; and

the reading the selected storage element occurs as part of a second step of the multi-step read operation.

4. The method of claim 3, wherein:

the multi-step read operation is an odd-even read operation in which storage elements associated with odd-numbered bit lines are read separately from storage elements associated with even-numbered bit lines.

5. The method of claim 1, wherein:

there are 2^N possible data states for the selected storage element, where N≧

2;

for one of the control gate read voltages which is associated with a lowest data state of the 2^N possible data states, the voltage of the respective bit line of the at least one bit line-adjacent storage element is adjusted to one of 2^N available levels; and

for one of the control gate read voltages which is associated with a next higher data state of the 2^N possible data states, the voltage of the respective bit line of the at least one bit line-adjacent storage element is adjusted to one of 2^N−

1 available levels.

6. The method of claim 1, wherein:

there are 2^N possible data states for the selected storage element, where N≧

2, and the voltage of the respective bit line of the at least one bit line-adjacent storage element is adjusted to one of more than 2^N available levels.

7. The method of claim 1, wherein:

the at least one bit line-adjacent storage element and the selected storage element are arranged along a common word line.

8. The method of claim 1, wherein:

the selected storage element is arranged along a selected word line, and the at least one bit line-adjacent storage element is arranged diagonally along an adjacent word line of the selected word line.

9. The method of claim 1, wherein:

different voltages are set on the respective bit line of the at least one bit line-adjacent storage element when corresponding different control gate read voltages are applied to the selected storage element.

10. The method of claim 1, wherein:

the different control gate read voltages include only one control gate read voltage for distinguishing between pairs of adjacent data states.

11. The method of claim 1, wherein:

the at least one bit line-adjacent storage element is an unselected storage element.

12. A non-volatile storage system which performs the method of claim 1.

13. A method for operating non-volatile storage, comprising:

as part of a first step of a multi-step read operation, reading a plurality of storage elements to ascertain their data states, the plurality of storage elements are associated with a plurality of adjacent bit lines; and

as part of a second step of the multi-step read operation, again reading the plurality of storage elements to again ascertain their data states, the again reading includes;

(a) applying different control gate read voltages, one after another, to the plurality of storage elements, and (b) setting voltages on the plurality of bit lines based on the ascertained data states of the first step and based on the control gate read voltages.

14. The method of claim 13, wherein:

for each control gate read voltage, the setting voltages comprises setting a voltage of each bit line according to whether or not the ascertained data state of the associated storage element from the first step corresponds to a data state associated with the control gate read voltage.

15. The method of claim 13, further comprising:

for each bit line, the set voltage is independent of the ascertained data state of the associated storage element from the first step when the data state associated with the control gate read voltage corresponds to the ascertained data state of the associated storage element from the first step, and the set voltage is dependent on the ascertained data state of the associated storage element from the first step when the data state associated with the control gate read voltage does not correspond to the ascertained data state of the associated storage element from the first step.

16. The method of claim 13, wherein:

the multi-step read operation is an all bit line read operation.

17. A non-volatile storage system which performs the method of claim 13.

18. A method for operating non-volatile storage, comprising:

reading storage elements on an adjacent word line of a selected word line to ascertain their data states, including reading a word-line adjacent storage element of a selected storage element, the selected storage element is associated with the selected word line and the word-line adjacent storage element is associated with a word line which is adjacent to the selected word line;

reading at least one bit line-adjacent storage element of the selected storage element, the at least one bit line-adjacent storage element is associated with a bit line which is adjacent to a bit line with which the selected storage element is associated; and

reading the selected storage element to ascertain its data state, while compensating for coupling to the selected storage element from the word line-adjacent storage element, responsive to the reading of the word line-adjacent storage element, and while compensating for coupling to the selected storage element from the at least one bit line-adjacent storage element, responsive to the reading of the at least one bit line-adjacent storage element.

19. The method of claim 18, wherein:

the compensating for coupling to the selected storage element from the at least one bit line-adjacent storage element comprises adjusting a voltage of a respective bit line of the at least one bit line-adjacent storage element based on its ascertained data state.

20. The method of claim 18, wherein:

the compensating for coupling to the selected storage element from the word line-adjacent storage element comprises applying a series of read pass voltages to the adjacent word line while applying each voltage of a plurality of control gate read voltages to the selected word line, and sensing the selected storage element when an identified one of the read pass voltages is applied, the identified one of the read pass voltages is based on the ascertained data state of the word line-adjacent storage element.

21. The method of claim 18, wherein:

the adjacent word line is after the selected word line in a programming order.

22. The method of claim 18, wherein:

the at least one bit line-adjacent storage element is arranged on the selected word line.

23. The method of claim 18, wherein:

the at least one bit line-adjacent storage element is arranged diagonally on the adjacent word line.

24. The method of claim 18, wherein:

the word-line adjacent storage element and the at least one bit line-adjacent storage element are unselected storage elements.

25. A non-volatile storage system which performs the method of claim 18.