Method of operating integrated circuit embedded with non-volatile programmable memory having variable coupling related application data

• US 7,876,615 B2
• Filed: 11/14/2008
• Issued: 01/25/2011
• Est. Priority Date: 11/14/2007
• Status: Expired due to Fees

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Jonker LLC
• Inventors: Liu, David, Gross, John Nicholas
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US12/271,680
• Publication Number:
  US 20090122604A1
• Time in Patent Office: 802 Days
• Field of Search: 365/185.03, 365/185.08, 365/185.18
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Claims

1. A method of operating a one-time programmable (OTP) single transistor device for storing at least one data bit situated on a substrate comprising:

providing a floating gate for the OTP single transistor device;

wherein said floating gate is comprised of a material that is also shared by an interconnect and/or another gate for a separate transistor device also situated on the substrate and associated with a separate logic gate and/or a volatile memory;

providing a source region for the OTP single transistor device; and

providing a drain region for the OTP single transistor device overlapping a variable areal portion of said floating gate and capacitively coupled thereto;

wherein an amount of capacitive coupling can be adjusted for the OTP single transistor device based on one of altering a number of N (N>

1) separate drain regions selected to overlap said floating gate and/or a variable programming voltage;

setting a threshold of said floating gate for the OTP single transistor device by selecting said variable programming voltage and/or which of said N separate drain regions provide a current of channel hot electrons.

2. The method of claim 1, wherein N=2 and said threshold of said floating gate can be set to one of four (4) different values.

3. The method of claim 1, wherein N=2 and said threshold of said floating gate can be set to one of three (3) different values.

4. The method of claim 1, wherein N=3 and said threshold of said floating gate can be set to one of eight (8) different values.

5. The method of claim 1, wherein N=2 and said threshold of said floating gate can be set to one of more than 2 but less than 8 different values.

6. The method of claim 1, wherein said threshold is determined by a read voltage applied to one or more of said N separate drain regions.

7. The method of claim 6, wherein said read voltage is controlled to have a range of values which vary in time corresponding to threshold states of said floating gate.

8. The method of claim 1, wherein said programming voltage causes the OTP single transistor device to change from a conducting state to a non-conducting state.

9. The method of claim 1, wherein said areal capacitive coupling takes place over a C-shaped area.

10. The method of claim 1, wherein the OTP single transistor device is part of a programmable memory array.

11. The method of claim 1, further including a step:

erasing the OTP single transistor device using band-band tunneling hot hole injection.

13. The method of claim 1, wherein said programming voltage causes the OTP single transistor device to change from a conducting state to a non-conducting state.

14. The method of claim 1, wherein said areal capacitive coupling takes place over a C-shaped area.

15. The method of claim 1, wherein the OTP single transistor device is part of a programmable memory array.

16. The method of claim 1, further including a step:

erasing the OTP single transistor device using band-band tunneling hot hole injection.

17. The method of claim 1, wherein N=2 and said threshold of said floating gate can be set to one of more than 2 but less than 8 different values.

12. A method of operating a one-time programmable (OTP) single transistor device situated on a substrate comprising:

providing a floating gate for the OTP single transistor device;

wherein said floating gate is comprised of a material that is also shared by an interconnect and/or another gate for a separate transistor device also situated on the substrate and associated with a separate logic gate and/or a volatile memory;

providing a source region for the OTP single transistor device coupled to a first source terminal; and

providing a drain region for the OTP single transistor device coupled to one or more second drain terminals and overlapping a variable areal portion of said floating gate and capacitively coupled to said floating gate;

wherein an amount of capacitive coupling can be adjusted for the OTP single transistor device based on one of altering a number of N (N>

1) separate drain regions selected to overlap said floating gate and/or a variable programming voltage;

setting a threshold of said floating gate for the OTP single transistor device by selecting said variable programming voltage applied across said first source terminal and said one or more second drain terminals, and/or selecting which of said N separate drain regions provide a current of channel hot electrons flowing between said first terminal and said one or more second terminals.