Hybrid scrambled transmission coding

• US 7,876,900 B1
• Filed: 05/23/2005
• Issued: 01/25/2011
• Est. Priority Date: 05/23/2005
• Status: Active Grant

• Current Assignee: Dell Marketing Corporation (Dell Technologies Inc.)
• Original Assignee: Force10 Networks, Inc. (Dell Technologies Inc.)
• Inventors: Goergen, Joel R.
• Primary Examiner(s): Moazzami; Nasser
• Assistant Examiner(s): McNally; Michael S
• Application Number:
  US11/135,482
• Time in Patent Office: 2,073 Days
• Field of Search: 380/255
• US Class Current: 380/255
• CPC Class Codes: H04K 1/00 Secret communication

Abstract

In one embodiment, a hybrid backplane coding scheme transmits data using lengthy sequences of scrambled data, separated by 8b/10b control character sequences that prepare the receiver for the next scrambled sequence and permit realignment if necessary. Advantageously, the sender of the scrambled data can be changed during the control character sequence. The hybrid backplane coding scheme can be designed such that the power spectral density of scrambled data and control character sequences are similar, which permits good performance with high-speed electrical differential receivers. Other embodiments are described and claimed.

Claims

1. A method of transmitting digital data sequences from a transmitting device to a receiving device across a serial channel, wherein the receiving device recovers the timing of the digital data sequences from the digital data sequence itself, the method comprising:

scrambling multiple digital data sequences;

sequentially transmitting the scrambled digital data sequences across the serial channel;

transmitting unscrambled channel control character sequences, each sequence comprising at least twenty bits, across the channel between the scrambled digital data sequences; and

measuring DC imbalance in one of the scrambled digital data sequences and selecting and inserting into the scrambled digital data sequence an additional unscrambled control character that counters the measured DC imbalance.

2. The method of claim 1, wherein each scrambled digital data sequence is at least ten times longer than the length of a scrambler used for scrambling that digital data segment.

3. The method of claim 2, wherein the scrambler length is less than 32 bits.

4. The method of claim 3, wherein the scrambling implements an X29+X19+1 scrambler.

5. The method of claim 1, wherein the scrambled digital data sequences have variable length but have start times spaced substantially evenly in time, the method further comprising, after each scrambled digital data sequence is transmitted, transmitting additional channel control characters across the channel as required to fill the remaining time until the start time for the following sequence.

6. The method of claim 1, wherein at least some of the channel control characters in each channel control character sequence are 8b/10b comma characters, the receiving device aligning its character timing with that of the transmitting device using the 8b/1 Ob comma characters.

7. The method of claim 1, wherein the transmitting device modifies the channel control character sequence to remove any DC bias present in the scrambled digital data sequence transmitted just prior to that channel control character sequence.

8. The method of claim 1, further comprising the transmitting device inserting at least one additional unscrambled control character within one of the scrambled digital data sequences prior to transmission.

9. The method of claim 1 further comprising measuring run length in one of the scrambled digital data sequences and inserting an additional unscrambled control character when the run length reaches a threshold.

10. The method of claim 1, further comprising, during transmission of each channel control character sequence, asserting a start-of-epoch signal to both the transmitting and the receiving devices, the transmitting device responding to an asserted start-of-epoch signal by transmitting a preamble channel control character pattern and then beginning transmission of the next scrambled digital data sequence.

11. The method of claim 10, further comprising the receiving device responding to an asserted start-of-epoch signal by receiving a preamble channel control character pattern and sending digital data received immediately after the preamble channel control character pattern to a descrambler.

12. The method of claim 10, wherein the transmitting and receiving device pair and corresponding channel are one of a plurality of similar transmitting and receiving device pairs and corresponding channels operating on parallel scrambled digital data sequences, each transmitting and receiving device in the plurality receiving the start-of-epoch signal.

13. The method of claim 12, further comprising switching the scrambled parallel digital data sequences between the transmitting and receiving devices, such that a different pairing of transmitting and receiving devices exists for two sequential scrambled data sequences transmitted by the same transmitting device.

14. The method of claim 13, wherein switching the parallel scrambled digital data sequences between the transmitting and receiving devices comprises pairing each transmitting device with an intermediate receiving device across a point-to-point dedicated channel, and pairing each receiving device with an intermediate sending device across a point-to-point dedicated channel, connecting the intermediate receiving and intermediate transmitting devices with a reconfigurable switch fabric, and configuring the reconfigurable switch fabric for each set of parallel digital data segments.

15. The method of claim 12, wherein for each received start-of-epoch signal, the plurality of similar transmitting devices are not required to each send the same length of scrambled digital data sequence.

16. The method of claim 1, further comprising the receiving device repeating at least one of the scrambled digital data sequences on a second channel to a second receiving device without descrambling the scrambled digital data sequence.

17. The method of claim 1, wherein scrambling each digital data sequence comprises initializing the scrambler with the same seed value for each sequence.

18. The method of claim 1, wherein transmitting an unscrambled channel control character sequence comprises transmitting an error checking value, the error checking value calculated over the scrambled digital data sequence preceding the unscrambled channel control character sequence.

19. The method of claim 18, wherein the error checking value is contained in an error-checking record having a first record character designated to indicate the presence of an error-checking record.

20. The method of claim 1, wherein transmitting an unscrambled channel control character sequence comprises transmitting a backchannel record following one of the scrambled digital data sequences, the backchannel record comprising parameters related to transmission across the serial channel.

21. The method of claim 20, wherein the backchannel record comprises a first record character designated to indicate the presence of the backchannel record.

22. A distributed packet switch comprising:

an electrical backplane comprising a plurality of differential signal trace pairs and a plurality of line cards and at least one switch fabric card coupled to the electrical backplane, each line card coupled to the at least one switch fabric card by at least two of the differential signal trace pairs, each of the differential signal trace pairs used for unidirectional communication either from a line card to a switch fabric card or from a switch fabric card to a line card, the line cards and switch fabric cards communicate digital data sequences across the differential signal trace pairs in a series of epochs, each epoch on a differential signal trace pair that is communicating a corresponding digital data sequence during that epoch comprising an unscrambled channel control character sequence of at least twenty bits and a scrambled version of the corresponding digital data sequence;

wherein the line cards comprise transmitters that measure DC imbalance in one of the scrambled digital data sequences and select and insert into the scrambled digital data sequence an additional unscrambled control character that counters the measured DC imbalance.

23. The distributed packet switch of claim 22, wherein the line cards each comprise scramblers for scrambling the digital data sequences, and wherein the at least one switch fabric card comprises a crossbar switch that repeats the scrambled versions of the digital data sequences received from the line cards, during each epoch, on differential signal trace pairs back to the line cards according to a crossbar configuration for that epoch.

24. The distributed packet switch of claim 23, wherein the scramblers use a scrambler length less than 32 bits.

25. The distributed packet switch of claim 24, wherein the scramblers implement X29+X19+1 scrambling.

26. The distributed packet switch of claim 23, wherein each line card transmits unscrambled channel control characters across its transmit differential signal pairs for the remainder of each epoch after completing sending the scrambled digital data sequence for that epoch.

27. The distributed packet switch of claim 22, wherein at least some of the channel control characters in each channel control character sequence are 8b/1 Ob comma characters, the line cards and at least one switch fabric card comprising receivers that use the 8b/1 Ob comma characters to align to the characters between scrambled digital data segments.

28. The distributed packet switch of claim 22, further comprising epoch-timing circuitry coupled to each line card and the at least one switch fabric card, the epoch-timing circuitry signaling the start of each epoch, each line card transmitting a preamble channel control character sequence after receiving a start-of-epoch signal from the epoch-timing circuitry before transmitting a scrambled digital data sequence for that epoch.