Simultaneous pipelined read with multiple level cache for improved system performance using flash technology
First Claim
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1. A command protocol method for a nonvolatile memory device, the command protocol method comprising:
- sending a first read command for one or more first pages of data to said nonvolatile memory device;
sending a first data address to said nonvolatile memory device, said nonvolatile memory device reading one or more first pages of data in accord with said first read command beginning at said first data address and loading said one or more first pages of data one page at a time from a memory array within said nonvolatile memory device into a data register that transfers the one or more first pages of data into a first level of a cache memory of said nonvolatile memory device with multiple page capacity, said cache memory having multiple levels within said nonvolatile memory device, said cache memory being separate from said data register, said data register having a capacity to store a single page of data, said data register and said cache memory controlled by control logic within said nonvolatile memory device such that said control logic controls the reading;
transferring the one or more first pages of data from the first level of the cache memory to a second level of the cache memory;
sending a second read command for one or more second pages of data to said nonvolatile memory device before receiving an entirety of the first pages of data located beginning at said first data address; and
sending a second data address to said nonvolatile memory device before receiving the entirety of first pages of data located beginning at said first data address, the nonvolatile memory device reading one or more second pages of data in accord with the second read command beginning at said second data address and loading the one or more second pages of data one page at a time via the data register into said first level of said cache memory while simultaneously outputting the one or more first pages of data from the second level of said cache memory to an input-output circuit within said nonvolatile memory device.
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Abstract
A read command protocol and a method of accessing a nonvolatile memory device having an internal cache memory. A memory device configured to accept a first and second read command, outputting a first requested data while simultaneously reading a second requested data. In addition, the memory device may be configured to send or receive a confirmation indicator.
30 Citations
29 Claims
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1. A command protocol method for a nonvolatile memory device, the command protocol method comprising:
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sending a first read command for one or more first pages of data to said nonvolatile memory device; sending a first data address to said nonvolatile memory device, said nonvolatile memory device reading one or more first pages of data in accord with said first read command beginning at said first data address and loading said one or more first pages of data one page at a time from a memory array within said nonvolatile memory device into a data register that transfers the one or more first pages of data into a first level of a cache memory of said nonvolatile memory device with multiple page capacity, said cache memory having multiple levels within said nonvolatile memory device, said cache memory being separate from said data register, said data register having a capacity to store a single page of data, said data register and said cache memory controlled by control logic within said nonvolatile memory device such that said control logic controls the reading; transferring the one or more first pages of data from the first level of the cache memory to a second level of the cache memory; sending a second read command for one or more second pages of data to said nonvolatile memory device before receiving an entirety of the first pages of data located beginning at said first data address; and sending a second data address to said nonvolatile memory device before receiving the entirety of first pages of data located beginning at said first data address, the nonvolatile memory device reading one or more second pages of data in accord with the second read command beginning at said second data address and loading the one or more second pages of data one page at a time via the data register into said first level of said cache memory while simultaneously outputting the one or more first pages of data from the second level of said cache memory to an input-output circuit within said nonvolatile memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of reading from a nonvolatile memory device, the method comprising:
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receiving, at the nonvolatile memory device, a first read command and a first memory address from a microprocessor coupled to said nonvolatile memory device; setting a read verification indicator in response to said first read command; reading a first plurality of data pages from a memory array one page at a time into a data register, said data register located within said nonvolatile memory device, said data register having a capacity to store a single page of data, said nonvolatile memory device having a cache memory within said nonvolatile memory device, said cache memory being separate from said data register, said data register and cache memory controlled by control logic within said nonvolatile memory device such that said control logic controls the reading; copying said first plurality of data pages from said data register, as each page is read from said memory array, into a first level cache of said cache memory within said nonvolatile memory device, said cache memory having multiple page capacity and having multiple level caches within said nonvolatile memory device; transferring the first plurality of data pages from the first level cache of said cache memory to a second level cache of said cache memory; receiving, at the nonvolatile memory device, a second read command and second memory address from the microprocessor; setting said read verification indicator in response to said second read command; and outputting said first plurality of data pages from the second level cache of said cache memory to an input-output circuit within said nonvolatile memory device to the microprocessor while simultaneously reading a second plurality of data pages from said memory array one page at a time into said data register and copying said second plurality of data pages into said first level cache as each page is read from said memory array. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method of reading from a nonvolatile memory device, the method comprising:
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reading at least one page of data from a nonvolatile memory array automatically one page at a time into a page register, the page register within said nonvolatile memory device, said nonvolatile memory device having a multi-page cache memory within said nonvolatile memory device, said multi-page cache memory being separate from said page register, said page register having a capacity to store a single page of data, said page register and multi-page cache memory controlled by control logic within said nonvolatile memory device such that said control logic controls the reading; copying said at least one page of data one page at a time from said page register to a first level cache of said multi-page cache memory of said nonvolatile memory device; transferring the at least one page data from said first level cache of said multi-page ache memory to a second level cache of said multi-page cache memory; copying a plurality of bits from said at least one page of data between the second level cache of said multi-page cache memory and an input-output circuit; and outputting, to an input-output circuit of said nonvolatile memory device, at least one bit of said plurality of bits from said at least one page of data and simultaneously reading at least one other page of data from said nonvolatile memory array automatically via said page register, into said first level cache of said multi-page cache memory. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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Specification