Continuous application and decompression of test patterns to a circuit-under-test

• US 7,877,656 B2
• Filed: 01/13/2009
• Issued: 01/25/2011
• Est. Priority Date: 11/23/1999
• Status: Expired due to Fees

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mukherjee, Nilanjan, Tyszer, Jerzy, Rajski, Janusz, Kassab, Mark
• Primary Examiner(s): Chung; Phung M
• Application Number:
  US12/352,994
• Publication Number:
  US 20090183041A1
• Time in Patent Office: 742 Days
• Field of Search: 714/724, 714/726, 714/729, 714/30, 714/738, 714/733, 714/734, 716/4
• US Class Current: 714/729
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear feedbackstate machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.

Claims

1. A method, comprising:

receiving a compressed test pattern of bits at one or more input channels of a decompressor;

decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being received by the decompressor; and

applying the decompressed test pattern to scan chains of the circuit-under-test,

wherein the number of the one or more input channels is fewer than the number of the scan chains to which the decompressed test pattern is applied, and

wherein the decompressing the compressed test pattern comprises logically combining bits of the compressed test pattern with bits stored in the decompressor and generating during a time period a greater number of decompressed test pattern bits than the number of compressed test pattern bits provided to the decompressor during the same time period.

2. The method of claim 1, further comprising applying the decompressed test pattern to scan chains of the circuit-under-test as the compressed test pattern is being provided.

3. The method of claim 1, wherein the providing the compressed test pattern, the decompressing the compressed test pattern, and the applying the decompressed pattern are performed synchronously at a same clock rate.

4. The method of claim 1, wherein the compressed test pattern is provided at a lower clock rate and the compressed test pattern is decompressed and applied synchronously at a higher clock rate.

5. The method of claim 1, wherein the compressed pattern is provided and decompressed at a higher clock rate and the decompressed pattern is applied synchronously at a lower clock rate.

6. The method of claim 1, wherein the greater number of bits is generated at a number of decompressor outputs, the number of decompressor outputs being greater than the number of inputs to which the compressed test pattern bits are provided.

7. The method of claim 1, wherein the greater number of bits is generated by generating the decompressed test pattern bits at a higher clock rate than the clock rate at which the compressed test pattern bits are provided.

8. The method of claim 1, wherein the providing the compressed test pattern comprises generating a serial stream of bits at a tester and applying the serial stream to one of the one or more input channels of the decompressor.

9. The method of claim 1, wherein the providing the compressed test pattern comprises generating a parallel stream of bits at a tester, converting the parallel stream to a serial stream, and applying the serial stream to one of the one or more input channels of the decompressor.

10. The method of claim 1, wherein the compressed test pattern is a deterministic test pattern.

11. The method of claim 1, wherein the compressed test pattern is provided by automatic testing equipment.

12. The method of claim 1, further including loading a register with the compressed test pattern, the register being positioned between the decompressor and automatic testing equipment.

13. A circuit, comprising:

a decompressor adapted to receive a compressed test pattern of bits and decompress the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received by the decompressor, the number of bits in the compressed test pattern being less than the number of bits in the decompressed test pattern, the decompressor comprising one or more input logic gates adapted to receive the compressed test pattern of bits and logically combine the compressed test pattern of bits with bits stored within the decompressor; and

scan chains for testing circuit logic, the scan chains being coupled to the decompressor and adapted to receive the decompressed test pattern, the number of scan chains coupled to the decompressor being greater than the number of input logic gates.

14. The circuit of claim 13, wherein the decompressor comprises a linear finite state machine adapted to receive the compressed test pattern.

15. The circuit of claim 14, wherein the decompressor includes a phase shifter coupled between the linear finite state machine and the scan chains.

16. The circuit of claim 15, wherein the phase shifter comprises an array of XOR or XNOR gates.

17. The circuit of claim 13, further comprising one or more registers coupled to respective inputs of the decompressor and adapted to provide the compressed test pattern of bits to the decompressor.

18. The circuit of claim 13, wherein the decompressor has a plurality of input channels and a plurality of outputs, the input channels receiving in parallel the bits of the compressed test patterns.

19. The circuit of claim 13, wherein the one or more input logic gates are XOR or XNOR gates.