Secured verification of configuration data for field programmable gate array devices

• US 7,878,902 B2
• Filed: 07/16/2003
• Issued: 02/01/2011
• Est. Priority Date: 07/16/2003
• Status: Active Grant

• Current Assignee: IGT (International Game Technology)
• Original Assignee: IGT (International Game Technology)
• Inventors: Griswold, Chauncey W., Mattice, Harold E., Wilder, Richard
• Primary Examiner(s): Vo; Peter DungBa
• Assistant Examiner(s): DEODHAR, OMKAR A
• Application Number:
  US10/621,873
• Publication Number:
  US 20050014559A1
• Time in Patent Office: 2,757 Days
• Field of Search: 463/29
• US Class Current: 463/29
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 2221/2109 Game systems
• CPC Class Codes: G07F 17/32 for games, toys, sports, or amusements
• CPC Class Codes: G07F 17/3241 Security aspects of a gaming system, e.g. detecting cheating, device integrity, surveillance computer security G06F21/00

Abstract

A method and apparatus for providing automated and secured verification of configuration data for a volatile progrannmable electronic device, such as an FPGA, is disclosed. A configurator including at least one memory unit, such as a ROM or EEPROM, contains a configuration file, which file is transferred to the volatile programmable electronic device or FPGA on demand. Data from the configuration file is compared with data from a separate custodial file, which custodial file is substantially identical to the configuration file and resides in a location separate from the memory unit or units that store the actual configuration file. In some instances the comparison is made before any actual loading of the configuration file into the FPGA occurs, whereby loading is prohibited if no match is confirmed, while in other instances the FPGA is configured using the configuration file and is then shut down if no match is later confirmed.

Claims

1. A method of authenticating configuration data within or about a gaming machine with respect to a gaming machine boot process, the method comprising:

configuring a central processing unit to execute executable programming instructions to generate a wager-based game on the gaming machine;

storing the executable programming instructions in a memory device for generating the wager-based game;

connecting a volatile programmable electronic device comprising a plurality of logic elements programmable to form logic gates in a communication path between the central processing unit and the memory device;

monitoring a communication between the central processing unit and at least one of an input device and an output device by using the volatile programmable electronic device;

storing instructions for configuring the volatile programmable electronic device to enable communications between the central processing unit and the memory device, wherein said storing instructions comprises storing the instructions within a read only configuration file included within a configurator;

accessing a separate read only custodial file, wherein at least a substantial portion of said custodial file is identical to at least a substantial portion of said configuration file when said configuration file is authentic, said custodial file residing in a location separate from said configurator;

determining whether to hold said volatile programmable electronic device in a reset mode;

if the reset mode is held, holding a plurality of operating contents of said volatile programmable electronic device as substantially empty upon a shut down phase of said gaming machine to disable communication between the central processing unit and the memory device;

booting up said gaming machine after said shut down phase;

transferring said configuration file from said configurator to said volatile programmable electronic device;

comparing at least a representative portion of data from said configuration file with at least a representative portion of data from said custodial file;

confirming whether said configuration file has been successfully compared to said custodial file;

continuing to hold said volatile programmable electronic device in the reset mode until said confirming of said successful comparison is completed;

configuring said volatile programmable electronic device with said configuration file;

permitting a substantial amount of regular gaming machine operations only after confirming that said configuration file has been successfully compared to said custodial file; and

facilitating communication between said memory device and said central processing unit upon said confirming that said configuration file has been successfully compared to said custodial file.

2. The method of claim 1, wherein said storing the instructions within a read only configuration file included within a configurator comprises storing the instructions within a read only configuration file included within the configurator that comprises a memory unit.

3. The method of claim 2, wherein said storing the instructions within a read only configuration file included within a configurator comprises storing the instructions within a read only configuration file included within the configurator having a memory unit that comprises a standard Read Only Memory.

4. The method of claim 2, wherein said storing the instructions within a read only configuration file included within a configurator comprises storing the instructions within a read only configuration file included within the configurator having a memory unit that comprises an Electrical Erasable Programmable Read Only Memory.

5. The method of claim 1, wherein said connecting a volatile programmable electronic device comprises connecting a Field Programmable Gate Array in the communication path between the central processing unit and the memory device.

6. The method of claim 1, wherein said connecting a volatile programmable electronic device comprises connecting a Simple Programmable Logic Device or a Complex Programmable Logic Device in the communication path between the central processing unit and the memory device.

7. The method of claim 1, wherein said central processing unit, said volatile programmable electronic device and said configurator all reside within the gaming machine.

8. The method of claim 1, wherein said comparing at least a representative portion is performed by said central processing unit.

9. The method of claim 8, wherein said custodial file is located within said central processing unit.

10. The method of claim 1, wherein said confirming step is performed prior to said transferring step.

11. The method of claim 1, wherein said configurator is located within said central processing unit.

12. The method of claim 1, further comprising determining not to facilitate communication between said memory device and said central processing unit upon determining that said configuration file has been unsuccessfully compared to said custodial file.

13. The method of claim 1, further comprising taking said volatile programmable electronic device out of the reset mode upon said confirming that said configuration file is successfully compared to said custodial file.

14. A microprocessor based gaming machine, comprising:

a central processing unit designed or configured to execute executable programming instructions used to generate a wager-based game on the microprocessor based gaming machine;

at least one of an input device and an output device;

a memory device used in conjunction with the microprocessor based gaming machine, said memory device configured to store the executable programming instructions for generating the wager-based game;

a volatile programmable electronic device, said volatile programmable electronic device comprising a plurality of logic elements programmable to form logic gates, said volatile programmable volatile programmable electronic device disposed in a communication path between the central processing unit and the memory device, said volatile programmable electronic device configured to monitor a communication between the central processing unit and said at least one of said input device and said output device, wherein said central processing unit is configured to determine whether to hold said volatile programmable electronic device in a reset mode;

a configurator;

a read only configuration file located within said configurator and adapted to be used in configuring said volatile programmable electronic device, said read only configuration file comprising instructions for configuring the volatile programmable electronic device to enable communications between the central processing unit and the memory device;

a separate custodial file located within the microprocessor based gaming machine and separate from said configurator, wherein at least a substantial portion of said separate custodial file is identical to at least a substantial portion of said configuration file; and

a comparator designed to compare at least a representative portion of data from said configuration file with at least a representative portion of data from said custodial file to authenticate said configuration file, said comparator adapted to provide a signal to said central processing unit regarding the results of said comparison, said central processing unit configured to continue to determine whether to hold said volatile programmable electronic device in the reset mode until the authentication is completed, said volatile programmable electronic device configured to facilitate communication between said memory device and said central processing unit based on the results of said comparison.

15. The microprocessor based gaming machine of claim 14, wherein said volatile programmable electronic device comprises a Field Programmable Gate Array.

16. The microprocessor based gaming machine of claim 14, wherein said configurator comprises an Electrical Erasable Programmable Read Only Memory.

17. The microprocessor based gaming machine of claim 14, wherein said comparator is located within said central processing unit.

18. The microprocessor based gaming machine of claim 14, wherein said custodial file is located within said central processing unit.

19. The microprocessor based gaming machine of claim 14, wherein said configurator is located within said central processing unit.

20. The microprocessor based gaming machine of claim 14, wherein said input device comprises a coin in switch or an input switch, and said output device comprises a video display or a speaker.

21. The microprocessor based gaming machine of claim 14, wherein said central processing unit is configured to take said volatile programmable electronic device out of the reset mode upon determining that the authentication including a successful comparison of said configuration file to said custodial file is completed.

22. A method of authenticating configuration data in a microprocessor based machine during a machine boot process, comprising:

configuring a central processing unit to execute executable programming instructions for generating a wager-based game on the microprocessor based machine;

storing the executable programming instructions in a memory device to generate the wager-based game;

determining whether to hold said primary volatile programmable electronic device in a reset mode;

holding a plurality of operating contents of a primary volatile programmable electronic device associated with the microprocessor based machine as substantially empty upon a shut down phase of the microprocessor based machine, wherein said holding the operating contents comprises holding the operating contents of the primary volatile programmable electronic device including a plurality of logic elements programmable to form logic gates;

disposing the primary volatile programmable electronic device in a communication path between the central processing unit and the memory device;

monitoring a communication between the central processing unit and at least one of an input device and an output device by using the primary volatile programmable electronic device;

disabling communication between the central processing unit and the memory device by performing said holding of the operating contents of the primary volatile programmable electronic device;

booting up the microprocessor based machine after said shut down phase;

transferring a read only configuration file to said volatile programmable electronic device, said read only configuration file comprising instructions for configuring the volatile programmable electronic device to enable communications between the central processing unit and the memory device;

comparing at least a representative portion of data from said configuration file with at least a representative portion of data from a separate custodial file,

wherein at least a substantial portion of said separate custodial file is identical to at least a substantial portion of said configuration file,

and wherein said separate custodial file resides in a location separate from said memory device;

confirming whether said configuration file has been successfully compared to said custodial file;

determining to continue said holding of said volatile programmable electronic device in the reset mode until said confirming of said successful comparison is completed;

configuring said volatile programmable electronic device with said configuration file;

permitting a substantial amount of regular microprocessor based machine operations only after said confirming that said configuration file has been successfully compared to said custodial file; and

facilitating communication between said memory device and said central processing unit upon said confirming that said configuration file has been successfully compared to said custodial file.

23. The method of claim 22, further comprising taking said volatile programmable electronic device out of the reset mode upon said confirming that said configuration file is successfully compared to said custodial file.

24. A method of authenticating data in a microprocessor based machine, comprising:

configuring a central processing unit (CPU) within the microprocessor based machine to execute executable programming instructions for generating a wager-based game on the microprocessor based machine;

storing the executable programming instructions in a memory device within the microprocessor based machine to generate the wager-based game;

disposing a field programmable gate array (FPGA) in a communication path between the CPU and the memory device, said FPGA located within the microprocessor based machine, and said FPGA comprising a plurality of logic elements programmable to form logic gates;

monitoring a communication between the CPU and at least one of an input device and an output device by using the FPGA;

storing a configuration file within a configurating EEPROM located within the microprocessor based machine, said configuration file comprising instructions for configuring the FPGA to enable communications between the CPU and the memory device;

storing a separate custodial file within the microprocessor based machine and separate from said EEPROM, wherein at least a substantial portion of said separate custodial file is identical to at least a substantial portion of said configuration file;

determining whether to hold said FPGA in a reset mode;

holding a plurality of operating contents of said FPGA as substantially empty upon a shut down phase of the microprocessor based machine to disable communication between the CPU and the memory device;

booting up the microprocessor based machine;

initiating a request to transfer said configuration file from said EEPROM to said FPGA;

utilizing said CPU to compare at least a representative portion of data from said configuration file with at least a representative portion of data from a separate custodial file;

confirming whether said configuration file has been successfully compared to said custodial file satisfaction;

determining to continue said holding of said FPGA in the reset mode until said confirming of said successful comparison is completed;

configuring said FPGA with said configuration file; and

facilitating communication between said memory device and said CPU upon said confirming that said configuration file has been successfully compared to said custodial file.

25. The method of claim 24, further comprising taking said FPGA out of the reset mode upon said confirming that said configuration file is successfully compared to said custodial file.