Field effect transistor with metal source/drain regions

• US 7,879,675 B2
• Filed: 05/02/2008
• Issued: 02/01/2011
• Est. Priority Date: 03/14/2005
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Majumdar, Amian, Chau, Robert S., Radosavljevic, Marko, Doczy, Mark L., Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Datta, Suman
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): KING, SUN MI KIM
• Application Number:
  US12/114,227
• Publication Number:
  US 20090325350A1
• Time in Patent Office: 1,005 Days
• Field of Search: 257/E21.425, 257/902, 257/E21.431, 438/268, 438/300
• US Class Current: 438/268
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.

Claims

1. A method of forming a transistor comprising:

forming a gate electrode having a pair of laterally opposite sidewalls on a gate dielectric layer formed on a semiconductor layer;

forming a pair of source/drain extensions in said semiconductor layer on opposite sides of said gate electrode;

forming a pair of sidewall spacers adjacent to said sidewalls of said gate electrode and on said source/drain extensions;

forming a pair of source/drain contact regions in said semiconductor layer on opposite sides of said sidewall spacers;

forming an interlayer dielectric adjacent to said sidewall spacers and over said source/drain contact regions;

etching a pair of contact openings through said interlayer dielectric to expose a portion of said source/drain contact regions;

etching away a portion of said source/drain contact regions to form a pair of etched-out source/drain contact regions, each etched-out source/drain contact region having an opening into said semiconductor layer, wherein each opening into said semiconductor layer is larger than each of the pair of contact openings formed through said interlayer dielectric; and

depositing a metal film into said contact openings and into said etched-out source/drain contact regions.

2. The method of claim 1 wherein said metal film in said etched-out source/drain contact regions directly contacts said source/drain extensions.

3. The method of claim 1 wherein said metal film is formed beneath said sidewall spacers.

4. The method of claim 1 wherein said source/drain extensions are formed by ion implanting dopants in alignment with said sidewalls of said gate electrode.

5. The method of claim 1 wherein said source/drain contact regions are formed by ion implanting dopants into said semiconductor film in alignment with the outside edges of said sidewall spacers.

6. A method of forming a nonplanar transistor comprising:

forming a semiconductor body having a top surface opposite a bottom surface formed on an insulating layer of an insulating substrate, said semiconductor body having a pair of laterally opposite sidewalls;

forming a gate dielectric layer on the top surface and sidewalls of said semiconductor body;

forming a gate electrode having a pair of laterally opposite sidewalls on said gate dielectric layer and on the top surface of said semiconductor body and adjacent to said gate dielectric layer on said sidewalls of said semiconductor body;

forming a pair of source/drain extensions in said semiconductor body on opposite sides of said gate electrode;

forming a pair of sidewalls spacers adjacent to said gate electrode and on and adjacent to said source/drain extensions formed in said semiconductor body;

forming a pair of source/drain contact regions in said semiconductor body on opposite sides of said sidewall spacers;

forming an interlayer dielectric layer over and adjacent to said semiconductor body and adjacent to said sidewall spacers;

etching a pair of contact openings through said interlayer dielectric layer to said source/drain contact regions in said semiconductor body;

etching away a portion of said source/drain contact regions in said semiconductor body, wherein said etching of said portion of said source/drain contact regions in said semiconductor body etches until said insulating layer of said insulating substrate is reached; and

depositing a metal film in said contact openings and in said etched away portion of said semiconductor body.

7. The method of claim 6 wherein said metal film in said etched away portion of said semiconductor body contacts said source/drain extension regions.

8. A method of forming a nonplanar transistor comprising:

forming a semiconductor body having a top surface opposite a bottom surface formed on an insulating layer of an insulating substrate, said semiconductor body having a pair of laterally opposite sidewalls;

forming a gate dielectric layer on the top surface and sidewalls of said semiconductor body;

forming a gate electrode having a pair of laterally opposite sidewalls on said gate dielectric layer and on the top surface of said semiconductor body and adjacent to said gate dielectric layer on said sidewalls of said semiconductor body;

forming a pair of source/drain extensions in said semiconductor body on opposite sides of said gate electrode;

forming a pair of sidewalls spacers adjacent to said gate electrode and on and adjacent to said source/drain extensions formed in said semiconductor body;

forming a pair of source/drain contact regions in said semiconductor body on opposite sides of said sidewall spacers;

forming an interlayer dielectric layer over and adjacent to said semiconductor body and adjacent to said sidewall spacers;

etching a pair of contact openings through said interlayer dielectric layer to said source/drain contact regions in said semiconductor body;

etching away a portion of each of said source/drain contact regions in said semiconductor body to provide a pair of openings into said semiconductor body, wherein each opening of said pair of openings into said semiconductor body is larger than each of the contact openings formed through said interlayer dielectric; and

depositing a metal film in said contact openings and in said etched away portion of said semiconductor body.