System and method for applying a pre-gate plasma etch in a semiconductor device manufacturing process

• US 7,879,694 B1
• Filed: 04/14/2008
• Issued: 02/01/2011
• Est. Priority Date: 07/13/2004
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Foote, Richard W.
• Primary Examiner(s): Graybill; David E
• Application Number:
  US12/082,776
• Time in Patent Office: 1,023 Days
• Field of Search: None
• US Class Current: 438/474
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28238 with sacrificial oxide

Abstract

A system and method is described for applying a pre-gate plasma etch in a semiconductor device manufacturing process in order to increase the integrity of a subsequently grown gate oxide layer. During the manufacture of a semiconductor device a sacrificial oxide layer is grown over a silicon substrate. The pre-gate plasma etch process is applied to the sacrificial oxide layer. Then the sacrificial oxide layer is stripped away and a gate oxide layer is grown over the silicon substrate. The gate oxide layer has an increased integrity due to the application of the pre-gate plasma etch process.

Claims

1. A method for manufacturing a gate oxide layer during a manufacturing process of a semiconductor device, said method comprising the steps of:

growing a sacrificial oxide layer over a silicon substrate;

applying a pre-gate plasma etch process to said sacrificial oxide layer that does not substantially remove said sacrificial oxide layer;

stripping away said sacrificial oxide layer from said silicon substrate; and

growing said gate oxide layer over said silicon substrate.

2. The method as set forth in claim 1 wherein said pre-gate plasma etch process is capable of etching silicon and silicon nitride at an etch rate that does not substantially etch silicon dioxide.

3. The method as set forth in claim 1 wherein portions of said silicon substrate form a corner at an edge of a shallow trench etched within said silicon substrate.

4. The method as set forth in claim 1 wherein said step of applying said pre-gate plasma etch process reduces stress in said gate oxide layer.

5. The method as set forth in claim 1 further comprising a step of growing a layer of polysilicon over said gate oxide layer.

6. The method as set forth in claim 5 wherein said step of applying said pre-gate plasma etch process by preventing formation of a notch in said gate oxide layer.

7. The method as set forth in claim 5 wherein said step of applying said pre-gate plasma etch process prevents formation of contaminating elements located within a notch located within said gate oxide layer.

8. The method as set forth in claim 7 wherein said step of preventing formation of contaminating elements located within said notch in said gate oxide layer prevents weakness from occurring in said gate oxide layer.

9. The method as set forth in claim 5 wherein said step of applying said pre-gate plasma etch process prevents formation of damaged silicon in said silicon substrate.

10. The method as set forth in claim 5 wherein said step of applying said pre-gate plasma etch process prevents formation of an oxidation blocking silicon-carbide-oxynitride film.

11. The method as set forth in claim 5 wherein said step of applying said pre-gate plasma etch process prevents formation of a high field area at a corner of said silicon substrate.

12. A method for manufacturing a gate oxide layer during a manufacturing process of a shallow trench in a semiconductor device, said method comprising the steps of:

etching a shallow trench in a silicon substrate;

growing a liner oxide layer over said silicon substrate of said shallow trench;

depositing a layer of tetra-ethyl-oxysilane (TEOS) material in said shallow trench;

chemical mechanical polishing said TEOS material to a desired level;

growing a sacrificial oxide layer over surfaces of said silicon substrate not covered by said TEOS material;

applying a pre-gate plasma etch process to said sacrificial oxide layer that does not substantially remove said sacrificial oxide layer;

stripping away said sacrificial oxide layer from said silicon substrate; and

growing said gate oxide layer over said silicon substrate.

13. The method as set forth in claim 12 wherein said pre-gate plasma etch process is capable of etching silicon and silicon nitride at an etch rate that does not substantially etch silicon dioxide.

14. The method as set forth in claim 12 wherein portions of said silicon substrate form a corner at an edge of said shallow trench etched within said silicon substrate.

15. The method as set forth in claim 12 wherein said step of applying said pre-gate plasma etch process reduces stress between said gate oxide layer and said liner oxide layer.

16. The method as set forth in claim 12 further comprising a step of growing a layer of polysilicon over said gate oxide layer and over said TEOS material within said shallow trench.

17. The method as set forth in claim 16 herein said step of applying said pre-gate plasma etch process prevents formation of a notch in said gate oxide layer.

18. The method as set forth in claim 16 wherein said step of applying said pre-gate plasma etch process prevents formation of contaminating elements located within a notch in said gate oxide layer.

19. The method as set forth in claim 18 wherein said step of preventing formation of contaminating elements located within said notch in said gate oxide layer prevents weakness from occurring in said gate oxide layer.

20. The method as set forth in claim 16 wherein said step of applying said pre-gate plasma etch process prevents formation of damaged silicon in said silicon substrate.

21. The method as set forth in claim 16 wherein said step of applying said pre-gate plasma etch process prevents formation of an oxidation blocking silicon-carbide-oxynitride film.

22. The method as set forth in claim 16 wherein said step of applying said pre-gate plasma etch process prevents formation of a high field area at a corner of said silicon substrate.