Fast recovery reduced p-n junction rectifier

• US 7,880,166 B2
• Filed: 05/08/2007
• Issued: 02/01/2011
• Est. Priority Date: 05/10/2006
• Status: Expired due to Fees

• Current Assignee: Ho-Yuan Yu
• Original Assignee: Ho-Yuan Yu
• Inventors: Yu, Ho-Yuan
• Primary Examiner(s): Purvis; Sue A
• Assistant Examiner(s): AHMED, SELIM U
• Application Number:
  US11/801,023
• Publication Number:
  US 20070262304A1
• Time in Patent Office: 1,365 Days
• Field of Search: 257/44, 257/328, 257/480, 257/E29.327, 257/E29.338
• US Class Current: 257/44
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A fast recovery rectifier structure with the combination of Schottky structure to relieve the minority carriers during the forward bias condition for the further reduction of the reverse recovery time during switching in addition to the lifetime killer such as Pt, Au, and/or irradiation. This fast recovery rectifier uses unpolished substrates and thick impurity diffusion for low cost production. A reduced p-n junction structure with a heavily doped film is provided to terminate and shorten the p-n junction space charge region. This reduced p-n junction with less total charge in the p-n junction to further improve the reverse recovery time. This reduced p-n junction can be used alone, with the traditional lifetime killer method, with the Schottky structure and/or with the epitaxial substrate.

Claims

1. A rectifier device, which comprises:

a n-type semiconductor substrate being a wafer;

a top metal layer having a first side and a second side disposed above said semiconductor substrate;

a backside layer disposed immediately below said semiconductor substrate, diffusion to said backside layer using same polarity species as said semiconductor substrate;

one or more reduced p-n junction structures disposed between said top metal layer and said semiconductor substrate, wherein each of said reduced p-n junction structures has a thin film of first p-type doping on top of a second p-type doping and the doping concentration of said first p-type is higher than said second p-type to create an early termination at p-side such that a total charge within the depletion region of said p-n junction is reduced, wherein the interface between said top metal layer and said first p-type at p-side is an ohmic contact; and

a plurality of edge termination structures formed proximate said first side and said second side of said top metal layer, and above said semiconductor substrate for protection purpose and sustaining high voltage.

2. The rectifier device of claim 1, said semiconductor substrate further comprising diffusion of one or more lifetime killer materials selected from the group consisting of Pt and Au to improve reverse recovery time and forward voltage drop.

3. The rectifier device of claim 1, wherein said top metal layer includes one or more elements selected from the group consisting of Pt, Au, Ni, Mo, W, Cr and Ti.

4. The rectifier device of claim 1, wherein said top metal layer further comprising a barrier metal of TiW or TiN.

5. The rectifier device of claim 1, further comprising an epitaxial layer disposed between said top metal layer and said semiconductor substrate, said epitaxial layer having same polarity but lower doping concentration than said semiconductor substrate, wherein said one or more reduced p-n junction structures is disposed in said epitaxial layer.

6. The rectifier device of claim 1, wherein said one or more reduced p-n junction structures is a doped layer.

7. The rectifier device of claim 1, wherein said one or more reduced p-n junction structures is doped regions which are formed by masking during implantation or diffusion, wherein the doping concentration of said second p-type of said reduced p-n junction is about 2 to about 10 times of n region.

8. The rectifier device of claim 5, further comprising a diode structure disposed between said one or more reduced p-n junction structures and said epitaxial layer, wherein said diode structure has lower doping concentration than said one or more reduced p-n junction structures.

9. The rectifier device of claim 1, wherein said edge termination structures are passivation layers.

10. The rectifier device of claim 5, wherein said edge termination structures are guard rings disposed in said epitaxial layer for high voltage purpose.

11. The rectifier device of claim 10, further comprising an insulation layer of oxide silicon, said insulation layer disposed above and adjacent to each of said guard rings.

12. The rectifier device of claim 6, further comprising at least one etched structure in said reduced p-n junction structures to create Schottky contact, wherein the shape of said etched structure is selected from the group consisting of round, hexagon and stripe.

13. The rectifier device of claim 12, wherein the width of said etched structure is generally larger than twice the depth of said reduced p-n junction structures.

14. The rectifier device of claim 1, further comprising at least one etched structure in said backside layer and said bottom layer to create Schottky contact.

15. The rectifier device of claim 7, further comprising at least one masked Schottky contact region spaced apart by said reduced p-n junction structures.

16. A rectifier device for reducing reverse recovery time, which comprises:

a n-type semiconductor substrate being a wafer, wherein said semiconductor substrate including one or more lifetime killer materials selected from the group consisting of Pt and Au;

an epitaxial layer disposed above said semiconductor substrate, said epitaxial layer having same polarity but lower doping concentration than said semiconductor substrate;

a plurality of reduced p-n junction anodes disposed in said epitaxial layer, wherein each of said reduced p-n junction anodes having opposite polarity to said epitaxial layer and said reduced p-n junction has a thin film of first p-type doping on top of a second p-type doping and the doping concentration of said first p-type is higher than said second p-type to create an early termination at p-side such that a total charge within the depletion region of said p-n junction is reduced, and the doping concentration of said second p-type of said reduced p-n junction is about 2 to about 10 times of n region;

a plurality of Schottky contact regions disposed in said epitaxial layer and spaced apart by said p-n junction anodes, wherein said Schottky contact regions are the masked region of photo resist and oxide layer;

a top metal layer having a first side and a second side, disposed above said reduced p-n junction anodes, wherein said top metal layer including one or more materials selected from the group consisting of Pt, Au, Ni, Mo, W, Cr and Ti;

a plurality of guard rings disposed in said epitaxial layer and near said first side and second side of said top metal layer for high voltage purpose, wherein said guard rings having opposite polarity to said epitaxial layer;

an insulation layer of oxide silicon, said insulation layer disposed above and adjacent to each of said guard rings to protect said guard rings;

a backside layer having same polarity and disposed below said semiconductor substrate, wherein the doping concentration of said backside layer is higher than said semiconductor substrate; and

a bottom layer disposed below said backside layer and made by a metallization process or Ni plating.