Nonvolatile charge trap memory device having <100> crystal plane channel orientation

• US 7,880,219 B2
• Filed: 09/26/2007
• Issued: 02/01/2011
• Est. Priority Date: 05/25/2007
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Polishchuk, Igor, Levy, Sagy, Ramkumar, Krishnaswamy
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US11/904,470
• Publication Number:
  US 20080290398A1
• Time in Patent Office: 1,224 Days
• Field of Search: 257/324, 257/411, 257/E29.309, 257/E21.18, 438/287, 438/288
• US Class Current: 257/324
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with <100> crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.

Claims

1. An N-channel nonvolatile charge trap memory device, comprising:

a source region and a drain region formed in a P-type active region, wherein the source and drain region are of N-type conductivity;

an N-type channel region having a channel length with <

100>

crystal plane orientation between the source region and the drain region; and

a gate stack disposed above the channel region, the gate stack comprising a charge-trapping layer with a graded composition, wherein the gate stack further comprises a tunnel dielectric layer with substantially the same tunnel oxide thickness along the sidewall and top surface of the N-type channel region.

2. The nonvolatile charge trap memory device of claim 1, wherein the gate stack is a SONOS-type gate stack.

3. The nonvolatile charge trap memory device of claim 1, wherein the active region comprises silicon.

4. The nonvolatile charge trap memory device of claim 1, wherein the charge-trapping layer is a dielectric layer.

5. An N-channel nonvolatile charge trap memory device, comprising:

an isolation structure formed in a substrate, the isolation structure comprising a top surface;

a P-type active region formed in the substrate and adjacent to the isolation structure, the P-type active region comprising a top surface at a same height as the top surface of the isolation structure;

an N-type channel region formed in the P-type active region, wherein the N-type channel region has a channel length with <

100>

crystal plane orientation;

a source region and a drain region formed in the P-type active region, wherein the channel region is between the source region and the drain region, wherein the source region and drain region are of N-type conductivity; and

a gate stack disposed above the N-type channel region, wherein the gate stack further comprises a tunnel dielectric layer with substantially the same tunnel oxide thickness along the sidewall and top surface of the N-type channel region.

6. The nonvolatile charge trap memory device of claim 5, wherein the isolation structure comprises a liner oxide having approximately equal thickness on a sidewall and a bottom surface of the isolation structure.

7. The nonvolatile charge trap memory device of claim 5, wherein the gate stack is a SONOS-type gate stack.

8. The nonvolatile charge trap memory device of claim 5, wherein the P-type active region comprises silicon.

9. The nonvolatile charge trap memory device of claim 5, wherein the gate stack comprises a dielectric charge-trapping layer.

10. A method of fabricating an N-channel nonvolatile charge trap memory device, comprising:

forming an isolation region and P-type active region in a substrate, each having a top surface, wherein the P-type active region is adjacent to the isolation region, and wherein the top surface of the P-type active region is at a same height as the top surface of the isolation structure;

forming a gate stack above the P-type active region; and

forming a source region and a drain region in the P-type active region and on other side of the gate stack to provide an N-type channel region in the active region, wherein the N-type channel region has a channel length with <

100>

crystal plane orientation between the source region and the drain region, wherein the source region and the drain region are of N-type conductivity, wherein forming the gate stack further comprises forming a tunnel dielectric layer with substantially the same growth rate along the sidewall and top surface of the channel region.

11. The method of claim 10, wherein the gate stack is a SONOS-type gate stack.

12. The method of claim 11, wherein the P-type active region comprises silicon.