Latch-up free vertical TVS diode array structure using trench isolation
First Claim
1. A transient voltage suppressing TVS array comprising:
- a first high-side and a first-low side steering diodes of said TVS array formed as dopant regions of different conductivity types for constituting PN junctions in a semiconductor substrate;
an isolation trench disposed between said first high-side and said first-low side steering diodes disposed immediately on both sides of said isolation trench wherein said first high-side and said first low-side steering diodes are electrically connected in series to a common Input/output (I/O) terminal as a first I/O terminal pad; and
wherein said isolation trench covered by an insulation layer underneath said first I/O terminal pad and filled with an insulation material therein for isolating and preventing a latch-up of parasitic PNP or NPN transistor between said doped regions in said semiconductor substrate of different conductivity types for suppressing a snap back of a voltage on said common I/O terminal for suppressing a transient voltage;
a main Zener diode comprising a body region of a second conductivity type disposed in an epitaxial layer of a first conductivity and said Zener diode is disposed between said first and second low-side steering diodes isolated from said first and second high-side steering diodes by two of said isolation trenches wherein said Zener diode is electrically connected to a cathode terminal as a separate electrical terminal from said first and second I/O terminal pads;
at least two additional PN junctions disposed immediately adjacent to and isolated by a second isolation trench connected in series to a second input/output (I/O) terminal pad functioning respectively as a second high-side steering diode and a second low-side steering diode wherein said second isolation trench is covered with an insulation layer underneath said second I/O terminal pad and filled with an insulation material therein;
said semiconductor substrate further comprising a N-type substrate supporting said epitaxial layer of a N-type conductivity wherein said semiconductor substrate with an anode electrode disposed on a bottom surface of said substrate for connecting to a high voltage and said cathode electrode disposed on a top surface for connecting said Zener diode to a low voltage; and
a dopant region of a N-conductivity type in said P-body region for constituting a NPN transistor with said body region and said epitaxial layer wherein said dopant region of said N-conductivity type is disposed near a top surface of said semiconductor substrate for directly connecting to said cathode electrode and is triggered on by said main Zener diode to conduct a large transient current with a low resistance.
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Abstract
A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types.
40 Citations
2 Claims
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1. A transient voltage suppressing TVS array comprising:
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a first high-side and a first-low side steering diodes of said TVS array formed as dopant regions of different conductivity types for constituting PN junctions in a semiconductor substrate; an isolation trench disposed between said first high-side and said first-low side steering diodes disposed immediately on both sides of said isolation trench wherein said first high-side and said first low-side steering diodes are electrically connected in series to a common Input/output (I/O) terminal as a first I/O terminal pad; and
wherein said isolation trench covered by an insulation layer underneath said first I/O terminal pad and filled with an insulation material therein for isolating and preventing a latch-up of parasitic PNP or NPN transistor between said doped regions in said semiconductor substrate of different conductivity types for suppressing a snap back of a voltage on said common I/O terminal for suppressing a transient voltage;a main Zener diode comprising a body region of a second conductivity type disposed in an epitaxial layer of a first conductivity and said Zener diode is disposed between said first and second low-side steering diodes isolated from said first and second high-side steering diodes by two of said isolation trenches wherein said Zener diode is electrically connected to a cathode terminal as a separate electrical terminal from said first and second I/O terminal pads; at least two additional PN junctions disposed immediately adjacent to and isolated by a second isolation trench connected in series to a second input/output (I/O) terminal pad functioning respectively as a second high-side steering diode and a second low-side steering diode wherein said second isolation trench is covered with an insulation layer underneath said second I/O terminal pad and filled with an insulation material therein; said semiconductor substrate further comprising a N-type substrate supporting said epitaxial layer of a N-type conductivity wherein said semiconductor substrate with an anode electrode disposed on a bottom surface of said substrate for connecting to a high voltage and said cathode electrode disposed on a top surface for connecting said Zener diode to a low voltage; and a dopant region of a N-conductivity type in said P-body region for constituting a NPN transistor with said body region and said epitaxial layer wherein said dopant region of said N-conductivity type is disposed near a top surface of said semiconductor substrate for directly connecting to said cathode electrode and is triggered on by said main Zener diode to conduct a large transient current with a low resistance. - View Dependent Claims (2)
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Specification