Wafer integrated with permanent carrier and method therefor

• US 7,880,293 B2
• Filed: 03/25/2008
• Issued: 02/01/2011
• Est. Priority Date: 03/25/2008
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Han, Byung Joon, Heng, Kock Liang, Marimuthu, Pandi Chelvam, Suthiwongsunthorn, Nathapong
• Primary Examiner(s): Garber; Charles D
• Assistant Examiner(s): Abdelaziez; Yasser A
• Application Number:
  US12/055,171
• Publication Number:
  US 20090243083A1
• Time in Patent Office: 1,043 Days
• Field of Search: None
• US Class Current: 257/698
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer exposing the conductive layer, a second via formed in the carrier wafer exposing the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second passivation layers are deposited over the first and second metal layers. The first or second passivation layer has an etched portion to expose a portion of the first metal layer or second metal layer.

Claims

1. A method of making a semiconductor device, comprising:

providing a wafer for supporting the semiconductor device;

forming a conductive layer over a top surface of the wafer;

permanently bonding a carrier wafer over the conductive layer;

forming an interconnect structure within the wafer and the carrier wafer by,

forming a first via in the wafer exposing the conductive layer,

forming a second via in the carrier wafer exposing the conductive layer,

depositing a first metal layer over the first via, the first metal layer in electrical contact with the conductive layer, and

depositing a second metal layer over the second via, the second metal layer in electrical contact with the conductive layer;

depositing first and second passivation layers over the first and second metal layers; and

etching a portion of the first or second passivation layer to expose a portion of the first metal layer or second metal layer.

2. The method of claim 1, including connecting a semiconductor package over the etched portion of the first or second passivation layer.

3. The method of claim 2, including depositing underfill material between the semiconductor package and the etched portion of the first or second passivation layer.

4. The method of claim 2, including depositing an electro-magnetic interference shield over the semiconductor package.

5. The method of claim 1, wherein the carrier wafer includes a material selected from the group consisting of glass, silicon, silicon carbide, and ceramic.

6. The method of claim 1, wherein permanently bonding the carrier wafer over the active surface of the wafer includes an anodic bonding process.

7. The method of claim 1, wherein forming an interconnect structure within the wafer and the carrier wafer includes a fabrication process that exceeds approximately 350°

C.

8. A method of making a semiconductor device, comprising:

providing a wafer for supporting the semiconductor device;

forming a conductive layer over a top surface of the wafer;

permanently bonding a carrier wafer over the conductive layer, the carrier wafer including a material selected from the group consisting of glass, silicon, silicon carbide, and ceramic; and

forming an interconnect structure within the wafer and the carrier wafer by,

forming a first via in the wafer exposing the conductive layer,

forming a second via in the carrier wafer exposing the conductive layer,

depositing a first metal layer over the first via, the first metal layer in electrical contact with the conductive layer, and

depositing a second metal layer over the second via, the second metal layer in electrical contact with the conductive layer.

9. The method of claim 8, including:

depositing first and second passivation layers over the first and second metal layers; and

etching a portion of the first or second passivation layer to expose a portion of the first metal layer or second metal layer.

10. The method of claim 9, including:

forming an under bump metallization layer over the etched portion of the first or second passivation layer; and

forming solder bumps over the under bump metallization layer.

11. The method of claim 8, including connecting a semiconductor package to the first or second metal layer.

12. The method of claim 11, including depositing underfill material beneath the semiconductor package.

13. The method of claim 12, including depositing an electro-magnetic interference shield over the semiconductor package.

14. The method of claim 8, wherein permanently bonding the carrier wafer over the active surface of the wafer includes an anodic bonding process.

15. The method of claim 8, wherein forming an interconnect structure within the wafer and the carrier wafer includes a fabrication process that exceeds approximately 350°

C.

16. A method of making a semiconductor device, comprising:

providing a wafer for supporting the semiconductor device;

forming a conductive layer over a top surface of the wafer;

permanently bonding a carrier wafer over the conductive layer;

forming an interconnect structure within the wafer and the carrier wafer, the interconnect structure including first and second metal layers;

depositing first and second passivation layers over the first and second metal layers; and

etching a portion of the first or second passivation layer to expose a portion of the first metal layer or second metal layer.

17. The method of claim 16, wherein forming an interconnect structure within the wafer and the carrier wafer includes:

forming a first via in the wafer exposing the conductive layer;

forming a second via in the carrier wafer exposing the conductive layer;

depositing the first metal layer over the first via, the first metal layer in electrical contact with the conductive layer; and

depositing the second metal layer over the second via, the second metal layer in electrical contact with the conductive layer.

18. The method of claim 16, including connecting a semiconductor package over the etched portion of the first or second passivation layer.

19. The method of claim 16, wherein the carrier wafer includes a material selected from the group consisting of glass, silicon, silicon carbide, and ceramic.

20. The method of claim 19, wherein permanently bonding the carrier wafer over the active surface of the wafer includes an anodic bonding process.

21. The method of claim 16, wherein forming an interconnect structure within the wafer and the carrier wafer includes a fabrication process that exceeds approximately 350°

C.

22. A semiconductor device, comprising:

a wafer for supporting the semiconductor device;

a conductive layer formed over a top surface of the wafer;

a carrier wafer permanently bonded over the conductive layer;

an interconnect structure formed within the wafer and the carrier wafer, the interconnect structure including,

a first via formed in the wafer exposing the conductive layer,

a second via formed in the carrier wafer exposing the conductive layer,

a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and

a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer; and

first and second passivation layers deposited over the first and second metal layers, the first or second passivation layer having an etched portion to expose a portion of the first metal layer or second metal layer.

23. The semiconductor package of claim 22, including a semiconductor package connected over the etched portion of the first or second passivation layer.

24. The semiconductor package of claim 22, wherein the carrier wafer includes a material selected from the group consisting of glass, silicon, silicon carbide, and ceramic.

25. The semiconductor package of claim 22, wherein the interconnect structure is formed using a fabrication process that exceeds approximately 350°

C.