Post passivation interconnection schemes on top of the IC chips

• US 7,880,304 B2
• Filed: 02/13/2009
• Issued: 02/01/2011
• Est. Priority Date: 10/12/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Chou, Chien-Kang, Chou, Chiu-Ming, Lin, Mou-Shiung
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US12/370,617
• Publication Number:
  US 20090146305A1
• Time in Patent Office: 718 Days
• Field of Search: 257/690, 257/700, 257/750, 257758-760, 257/780, 257/781, 257/784, 257/E23.019, 257/E23.142
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. An integrated circuit chip comprising:

a silicon substrate;

a first internal circuit in and on said silicon substrate;

a second internal circuit in and on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit;

a passivation layer over said dielectric layer, wherein said passivation layer comprises a layer of nitrogen-containing compound;

a first via in said passivation layer, wherein said first via is connected to said first internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said passivation layer;

a second via in said passivation layer, wherein said second via is connected to said second internal circuit through said second interconnecting structure; and

a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square and having a thickness between 2 and 100 micrometers, wherein said third interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer and an electroplated metal layer on said seed layer, wherein said second adhesion layer is under a bottom of said electroplated metal layer, but is not at a sidewall of said electroplated metal layer.

2. The integrated circuit chip of claim 1, wherein said second adhesion layer comprises titanium.

3. The integrated circuit chip of claim 1, wherein said electroplated metal layer comprises electroplated gold.

4. The integrated circuit chip of claim 1, wherein said electroplated metal layer comprises electroplated copper.

5. The integrated circuit chip of claim 1, wherein an undercut with an edge of said second adhesion layer recessed from an edge of said electroplated metal layer is between 0.03 and 2 micrometers.

6. An integrated circuit chip comprising:

a silicon substrate;

an internal circuit in and on said silicon substrate;

an ESD circuit in and on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said internal circuit, wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said ESD circuit;

a passivation layer over said dielectric layer, wherein said passivation layer comprises a layer of a nitrogen-containing compound;

a first via in said passivation layer, wherein said first via is connected to said internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said passivation layer;

a second via in said passivation layer, wherein said second via is connected to said ESD circuit through said second interconnecting structure; and

a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said internal circuit is connected to said ESD circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square and having a thickness between 2 and 100 micrometers, wherein said third interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer and an electroplated metal layer on said seed layer, wherein said second adhesion layer is under a bottom of said electroplated metal layer, but is not at a sidewall of said electroplated metal layer.

7. The integrated circuit chip of claim 6, wherein said second adhesion layer comprises titanium.

8. The integrated circuit chip of claim 6, wherein said electroplated metal layer comprises electroplated gold.

9. The integrated circuit chip of claim 6, wherein said electroplated metal layer comprises electroplated copper.

10. The integrated circuit chip of claim 6, wherein said third interconnecting structure comprises a ground bus connecting said internal circuit to said ESD circuit.

11. An integrated circuit chip comprising:

a silicon substrate;

a first internal circuit in and on said silicon substrate;

a second internal circuit in and on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit;

an insulating layer over said dielectric layer;

a first via in said insulating layer, wherein said first via is connected to said first internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said insulating layer;

a second via in said insulating layer, wherein said second via is connected to said second internal circuit through said second interconnecting structure; and

a third interconnecting structure over said insulating layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, wherein said third interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer and an electroplated metal layer on said seed layer, wherein said second adhesion layer is under a bottom of said electroplated metal layer, but is not at a sidewall of said electroplated metal layer.

12. The integrated circuit chip of claim 11, wherein said second adhesion layer comprises titanium.

13. The integrated circuit chip of claim 11, wherein said electroplated metal layer comprises electroplated gold.

14. The integrated circuit chip of claim 11, wherein said electroplated metal layer comprises electroplated copper.

15. The integrated circuit chip of claim 11, wherein an undercut with an edge of said second adhesion layer recessed from an edge of said electroplated metal layer is between 0.03 and 2 micrometers.

16. An integrated circuit chip comprising:

a silicon substrate;

an internal circuit in and on said silicon substrate;

an ESD circuit in and on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said internal circuit, and wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said ESD circuit;

an insulating layer over said dielectric layer;

a first via in said insulating layer, wherein said first via is connected to said internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said insulating layer;

a second via in said insulating layer, wherein said second via is connected to said ESD circuit through said second interconnecting structure; and

a third interconnecting structure over said insulating layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said internal circuit is connected to said ESD circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, wherein said third interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer and an electroplated metal layer on said seed layer, wherein said second adhesion layer is under a bottom of said electroplated metal layer, but is not at a sidewall of said electroplated metal layer.

17. The integrated circuit chip of claim 16, wherein said second adhesion layer comprises titanium.

18. The integrated circuit chip of claim 16, wherein said electroplated metal layer comprises electroplated gold.

19. The integrated circuit chip of claim 16, wherein said electroplated metal layer comprises electroplated copper.

20. The integrated circuit chip of claim 16, wherein said third interconnecting structure comprises a ground bus connecting said internal circuit to said ESD circuit.

21. An integrated circuit chip comprising:

a silicon substrate;

a first internal circuit in and on said silicon substrate;

a second internal circuit in and on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, and wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit;

an insulating layer over said dielectric layer;

a first via in said insulating layer, wherein said first via is connected to said first internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said insulating layer;

a second via in said insulating layer, wherein said second via is connected to said second internal circuit through said second interconnecting structure;

a third interconnecting structure over said insulating layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, wherein said third interconnecting structure comprises a second adhesion layer and a metal layer over said second adhesion layer; and

a polymer layer over said insulating layer, wherein said polymer layer comprises a portion over said third interconnecting structure.

22. The integrated circuit chip of claim 21, wherein said second adhesion layer comprises titanium.

23. The integrated circuit chip of claim 21, wherein said metal layer of said third interconnecting structure comprises electroplated gold.

24. The integrated circuit chip of claim 21, wherein said metal layer of said third interconnecting structure comprises electroplated copper.

25. An integrated circuit chip comprising:

a silicon substrate;

an ESD circuit in and on said silicon substrate;

an internal circuit in and on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said internal circuit, and wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said ESD circuit;

an insulating layer over said dielectric layer;

a first via in said insulating layer, wherein said first via is connected to said internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said insulating layer;

a second via in said insulating layer, wherein said second via is connected to said ESD circuit through said second interconnecting structure;

a third interconnecting structure over said insulating layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said internal circuit is connected to said ESD circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, wherein said third interconnecting structure comprises a second adhesion layer and a metal layer over said second adhesion layer; and

a polymer layer over said insulating layer, wherein said polymer layer comprises a portion over said third interconnecting structure.

26. The integrated circuit chip of claim 25, wherein said second adhesion layer comprises titanium.

27. The integrated circuit chip of claim 25, wherein said metal layer of said third interconnecting structure comprises electroplated gold.

28. The integrated circuit chip of claim 25, wherein said metal layer of said third interconnecting structure comprises electroplated copper.