Accurate capacitance measurement for ultra large scale integrated circuits

• US 7,880,494 B2
• Filed: 03/02/2010
• Issued: 02/01/2011
• Est. Priority Date: 06/29/2007
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Sally, Chang, Victor Chih Yuan, Chang, Keh-Jeng, Doong, Yih-Yuh, Hung, Lien Jung, Mii, Yuh-Jier
• Primary Examiner(s): PATEL, PARESH H
• Application Number:
  US12/715,739
• Publication Number:
  US 20100156453A1
• Time in Patent Office: 336 Days
• Field of Search: None
• US Class Current: 324/762.02
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.

Claims

1. A method of measuring parasitic capacitance in a semiconductor, said method comprising:

providing a first test structure comprising a first conductive comb structure and a second conductive comb structure complementary to the first comb, each of said first and second conductive comb structures being formed in a first interconnect layer, and a third conductive comb structure and a fourth conductive comb structure complementary to the third comb, each said third and fourth conductive comb structures being formed in a second interconnect layer;

wherein the first conductive comb structure couples with the fourth conductive comb structure through a first plurality of to-be-measured via formed at the cross-over regions of the first and the fourth conductive comb structures, and the second conductive comb structure couples with the third conductive comb structure through a second plurality of to-be-measured via formed at the cross-over regions of the second and the third conductive comb structures;

applying a first bias to the first and the fourth conductive comb structures, and a second bias to the second and the third conductive comb structures;

measuring a first capacitance on said first test structure between said first bias and said second bias;

providing a second test structure comprising a fifth conductive comb structure and a sixth conductive comb structure complementary to the fifth conductive comb structure, both being formed in the first interconnect layer, and a seventh conductive comb structure and an eighth conductive comb structure complementary to the seventh conductive comb structure, both being formed in the second interconnect layer;

wherein the fifth and the eight conductive comb structures are substantially similar to the first and the fourth conductive comb structures, respectively, being free of to-be-measured vias formed between the fifth and the eight conductive comb structures;

wherein the sixth and the seventh conductive comb structures are substantially similar to the second and the third conductive comb structures, respectively, being free of to-be-measured vias formed between the sixth and the seventh conductive comb structures;

applying the first bias to the fifth and the eight conductive comb structures, and the second bias to the sixth and the seventh conductive comb structures;

measuring a second capacitance on the second test structure between the first bias and the second bias; and

calculating a parasitic capacitance C_v of to-be-measured via using said first and said second capacitances.

2. The method of claim 1, wherein said first and second test structures are formed on a semiconductor substrate comprising one of doped silicon, silicon germanium, gallium arsenide, compound semiconductor, multi-layers semiconductor, silicon on insulator (SOI), and any combination thereof.

3. The method of claim 1, wherein said first and said second plurality of to-be-measured via are through-silicon vias that couple said first interconnect layer in a first integrated circuit die with said second interconnect layer in a second integrated circuit die overlying said first integrated circuit die.

4. The method of claim 1, wherein said calculating includes deriving C_v from capacitance measured on said first capacitance (C_T) and said second capacitance (C_T—

_ref) according to the formula C_v=(C_T−

C<sub>T—

ref</sub>)/N, wherein N is the total number of said first plurality and said second plurality of to-be-measured vias in said first test structure.

5. The method of claim 1, wherein said steps of measuring said first and said second capacitance is performed by a passive capacitance measuring approach using at least an LCR meter.

6. The method of claim 1, wherein said step of measuring said first capacitance and said second capacitance is performed by an active capacitance measuring approach including a CBCM approach.