Low power reconfigurable circuits with delay compensation

• US 7,880,505 B2
• Filed: 02/19/2010
• Issued: 02/01/2011
• Est. Priority Date: 02/20/2009
• Status: Active Grant

• Current Assignee: Government of The United States, As Represented by The Director of The National Security Agency, Lawrence Livermore National Security LLC (Government of the United States of America), Texas A&M University System
• Original Assignee: Lawrence Livermore National Security LLC (Government of the United States of America)
• Inventors: Khatri, Sunil Papanchand, Griffin, Timothy Kevin, Vaidya, Sheila, Jayakumar, Nikhil
• Primary Examiner(s): Le; Don P
• Application Number:
  US12/709,227
• Publication Number:
  US 20100213978A1
• Time in Patent Office: 347 Days
• Field of Search: 326/21, 326 26- 28, 326 93- 98
• US Class Current: 326/93
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

According to one aspect of the present disclosure, a circuit includes a semiconductor device including a plurality of logic blocks and a plurality of programmable interconnects. A delay detector generates a delay signal responsive to a measured delay of an output signal, wherein the output signal is from at least one of the plurality of logic blocks. A biasing circuit responsive to the delay signal to adjust subsequent measured delays toward a predetermined value.

Claims

1. A circuit comprising:

a semiconductor device having a plurality of logic blocks and a plurality of programmable interconnects;

a delay detector for generating a delay signal responsive to a measured delay of an output signal, wherein the output signal is from at least one of the plurality of logic blocks, and

a biasing circuit responsive to the delay signal to adjust a subsequently measured delays toward a predetermined value.

2. The circuit of claim 1, wherein at least one of the plurality of logic blocks is operated with a sub-threshold voltage.

3. The circuit of claim 1, wherein the logic blocks or interconnects are programmable.

4. The circuit of claim 2, wherein the reference value is derived from a beat clock.

5. The circuit of claim 2, wherein the measured delay is derived by comparing a phase of the output signal to the phase of a beat clock.

6. The circuit of claim 2, wherein the semiconductor device is a field programmable gate array, wherein the delay detector includes a phase detector, and wherein the biasing circuit includes a charge pump.

7. The circuit of claim 6, wherein the phase detector includes a gofast output and a goslow output, wherein a first input to the charge pump is responsive to the gofast output, and wherein a second input to the charge pump is responsive the goslow output.

8. The circuit of claim 7, wherein a bulk voltage for the semiconductor device is responsive to a charge pump output.

9. A low power circuit comprising:

a field programmable gate array circuit including a reference block, wherein the reference block produces a reference output signal, wherein the reference output signal;

is a sub-threshold leakage current or voltage; and

includes a reference output signal phase,

a phase detector adapted to determine a delay by comparing the reference output signal phase to a reference delay signal; and

a charge pump responsive to an indication of the delay to bias the reference output signal toward the reference delay signal.

10. The circuit of claim 9, wherein the reference output signal switches in response to a clock signal provided to the reference block.

11. The circuit of claim 10, wherein the circuit is a dynamic body biasing circuit.

12. The circuit of claim 11, wherein the circuit includes a plurality of further blocks, wherein the circuit self-compensates a delay of the plurality of further blocks to approach the reference delay signal.

13. The circuit of claim 9, wherein the charge pump includes a charge pump output coupled directly or indirectly to a common bulk terminal of the field programmable gate array circuit.

14. The circuit of claim 13, wherein the charge pump output is responsive to an indication of a delay.

15. The circuit of claim 13, wherein the field programmable gate array circuit includes a lookup table, flip-flops, configurable logic blocks, or memories.

16. The circuit of claim 15, wherein the combinational lookup table is comprised of substantially all NMOS devices.

17. The circuit of claim 14, wherein the combinational lookup table comprises NMOS devices.

18. The circuit of claim 14, wherein a voltage of the charge pump output is increased if the indication of the delay includes information that rising edges of reference output signal occur after corresponding rising edges of the reference delay signal.

19. The circuit of claim 17, wherein the compensation is performed for Pbulk terminal alone, or for Nbulk and Pbulk terminals.

20. The circuit of claim 18, wherein a voltage of the charge pump output is decreased if the indication of the delay includes information that rising edges of the reference output signal occur before corresponding rising edges of the reference delay signal.

21. A method comprising the steps of:

operating a reference block within a field programmable gate array circuit at a sub-threshold level to produce an output, wherein the output has an output delay; and

dynamically biasing a portion of the FPGA to increase or decrease the output delay toward a predetermined delay.

22. The method of claim 21, wherein the step of dynamically biasing includes modulating a bulk terminal, wherein the predetermined delay is indicated by a reference delay signal, wherein the method further comprises:

comparing the reference delay signal to the output delay; and

adjusting an input voltage to the FPGA bulk terminal based on the comparison.

23. The method of claim 21, wherein the step of adjusting an input voltage includes a step of providing a further input to a charge pump to result in the input voltage increasing or decreasing.

24. The method of claim 22, wherein the step of comparing the reference delay signal to the output delay is performed by a phase detector.

25. The method of claim 21, wherein the FPGA circuit operates in a quasi-delay insensitive, micro-pipelined or asynchronous fashion.

26. The method of claim 21, wherein the FPGA circuit is realized using 3D integration.

27. The method of claim 21, wherein the FPGA circuit is realized using current mode operation.