Level Shifter, standard cell, system and method for level shifting

• US 7,880,526 B2
• Filed: 08/11/2008
• Issued: 02/01/2011
• Est. Priority Date: 08/11/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Acharya, Pramod
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US12/189,202
• Publication Number:
  US 20100033224A1
• Time in Patent Office: 904 Days
• Field of Search: 326 62- 63, 326 80- 81, 327/306, 327/333
• US Class Current: 327/333
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

Implementations are presented herein that include a level shifter circuit.

Claims

1. A level shifter circuit, comprising:

an input node configured to receive an input signal;

an inverted terminal and a non-inverted terminal;

a capacitor having at least two terminals, wherein at least a first terminal of the at least two terminals is coupled to the input node and at least a second terminal of the at least two terminals is coupled to one of the inverted terminal and the non-inverted terminal;

a latch circuit coupled to the input node, the latch circuit configured to provide a non-inverted signal at the non-inverted terminal and an inverted signal at the inverted terminal in response to a logic state of the input signal; and

a first switch device configured to provide a reference potential to the inverted terminal of the latch circuit in response to the logic state of the input signal,

wherein the level shifter circuit is formed in one well.

2. The level shifter circuit of claim 1, wherein the capacitor is a bootstrapping capacitor configured to provide a voltage level at the input node to the internal node.

3. The level shifter circuit of claim 1, further comprising an output node, the output node configured to provide an output signal having low and high voltage states, and wherein the input node is configured to receive an input signal having low and high voltage states, and further wherein a voltage level of the high voltage state of the output signal is different than a voltage level of the high voltage state of the input signal.

4. The level shifter circuit of claim 3, wherein the voltage level of the high voltage state of the input signal corresponds to a first supply voltage and the voltage level of the high voltage state of the output signal corresponds to a second supply voltage.

5. The level shifter circuit of claim 3, wherein a voltage level of the low voltage state of the output signal and a voltage level of the low voltage state of the input signal correspond to a reference potential.

6. The level shifter circuit of claim 1, wherein the internal node of the level shifter circuit is coupled to the non-inverted terminal of the latch circuit.

7. The level shifter circuit of claim 1, further comprising an output node, wherein the output node is coupled to the inverted terminal or the non-inverted terminal of the latch circuit.

8. The level shifter circuit of claim 1, further comprising an output stage coupled to the latch circuit, wherein the output stage is configured to provide an output signal in response to the logic state of the input signal.

9. The level shifter circuit of claim 1, wherein a voltage level of a high voltage state of the input signal corresponds to a first supply voltage and the latch circuit is coupled to a second supply voltage.

10. The level shifter circuit of claim 1, further comprising a second switch device configured to provide a voltage level at the input node to the non-inverted terminal of the latch circuit in response to a logic state of the inverted terminal of the latch circuit.

11. A method for level shifting in a level shifter circuit, comprising:

receiving an input signal;

providing a voltage level of the input signal to a boosted node using a capacitor coupled to one of a non-inverted node or an inverted node;

providing an output signal in response to a voltage level of the boosted node;

latching a non-inverted logic state of the input signal in the non-inverted node and latching an inverted logic state of the input signal in the inverted node in response to a logic state of the input signal; and

switching a reference potential to the inverted node in response to the logic state of the input signal,

wherein the level shifter circuit is formed in one well.

12. The method of claim 11, wherein the voltage level of the input signal is provided to the boosted node by using the capacitor coupled between the boosted node and an input node configured to receive the input signal.

13. The method of claim 11, wherein a voltage level of a high voltage state of the output signal is different than a voltage level of a high voltage state of the input signal or wherein a voltage level of a low voltage state of the output signal is different than a voltage level of a low voltage state of the input signal.

14. The method of claim 11, further comprising switching a voltage level at the input node to the non-inverted node in response to a logic state of the inverted node.