Enhancement-mode field effect transistor based electrostatic discharge protection circuit

• US 7,881,030 B1
• Filed: 07/07/2008
• Issued: 02/01/2011
• Est. Priority Date: 07/07/2008
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Peachey, Nathaniel, Li, Jason Yuxin, Muthukrishnan, Swaminathan, Iversen, Christian Rye, Wohlmuth, Walter A.
• Primary Examiner(s): Nguyen; Danny
• Application Number:
  US12/168,179
• Time in Patent Office: 939 Days
• Field of Search: 361/56, 361/58, 361/111
• US Class Current: 361/56
• CPC Class Codes: H01Q 1/50 Structural association of antennas with earthing switches, lead-in devices or lightning protectors
• CPC Class Codes: H03F 1/52 Circuit arrangements for protecting such amplifiers monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74
• CPC Class Codes: H03F 2200/441 Protection of an amplifier being implemented by clamping means

Abstract

The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance, a drain-to-gate resistance, or both of the FET element, and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element and a resistive element. Therefore, the single FET element ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

Claims

1. An electrostatic discharge (ESD) clamp circuit comprising:

a first terminal;

a second terminal having a first voltage with respect to a voltage at the first terminal, such that the first terminal and the second terminal are coupled between an ESD protected circuit and a direct current (DC) reference;

a first enhancement-mode field effect transistor (FET) element formed using a compound semiconductor material and comprising;

a first drain coupled to the first terminal;

a first source coupled to the second terminal; and

a first gate;

a first resistive element coupled between the first gate and the second terminal, wherein when the first voltage exceeds a first threshold, the ESD clamp circuit is in a clamping state; and

a plurality of resistive elements comprising the first resistive element,

wherein the first enhancement-mode FET element further comprises a multiple gate enhancement-mode FET element having a plurality of gates comprising the first gate, such that each of the plurality of resistive elements is coupled between a corresponding each of the plurality of gates and the second terminal.

2. The ESD clamp circuit of claim 1 wherein the compound semiconductor material comprises at least one selected from a group consisting of Gallium Arsenide, Indium Phosphide, and Gallium Nitride.

3. The ESD clamp circuit of claim 1 wherein the compound semiconductor material comprises at least one element selected from column III of a periodic table of the elements and at least one element selected from column V of the periodic table of the elements.

4. The ESD clamp circuit of claim 1 further comprising a series resistive element coupled between the first drain and the first terminal.

5. The ESD clamp circuit of claim 1 wherein the first drain is directly coupled to the first terminal.

6. The ESD clamp circuit of claim 1 wherein the ESD protected circuit comprises a signal input and the first terminal and the second terminal are coupled between the signal input and the DC reference.

7. The ESD clamp circuit of claim 1 wherein the ESD protected circuit comprises a signal output and the first terminal and the second terminal are coupled between the signal output and the DC reference.

8. The ESD clamp circuit of claim 1 wherein the ESD protected circuit comprises an impedance matching network.

9. The ESD clamp circuit of claim 1 wherein the DC reference is ground.

10. The ESD clamp circuit of claim 1 wherein the DC reference is a DC power supply.

11. The ESD clamp circuit of claim 1 wherein the first threshold is based on the first resistive element and a drain-to-gate capacitance of the first enhancement-mode FET element.

12. The ESD clamp circuit of claim 1 wherein the first threshold is based on the first resistive element, a drain-to-gate capacitance of the first enhancement-mode FET element, and a drain-to-gate resistance of the first enhancement-mode FET element.

13. The ESD clamp circuit of claim 1 wherein when the first voltage is positive and exceeds a second threshold, the ESD clamp circuit is in a clamping state, such that the second threshold is less than the first threshold.

14. The ESD clamp circuit of claim 1 wherein the multi-gate enhancement-mode FET is a multiple gate enhancement-mode pseudomorphic high electron mobility transistor (pHEMT) element.

15. An electrostatic discharge (ESD) clamp circuit comprising:

a first terminal;

a second terminal having a first voltage with respect to a voltage at the first terminal, such that the first terminal and the second terminal are coupled between an ESD protected circuit and a direct current (DC) reference;

a first enhancement-mode field effect transistor (FET) element formed using a compound semiconductor material and comprising;

a first drain coupled to the first terminal;

a first source coupled to the second terminal; and

a first gate;

a first resistive element coupled between the first gate and the second terminal,

wherein when the first voltage exceeds a first threshold, the ESD clamp circuit is in a clamping state; and

a plurality of resistive elements comprising the first resistive element, wherein the first enhancement-mode FET element further comprises a multiple gate enhancement-mode pseudomorphic high electron mobility transistor (pHEMT) element having a plurality of gates comprising the first gate, such that each of the plurality of resistive elements is coupled between a corresponding each of the plurality of gates and the second terminal.

16. An electrostatic discharge (ESD) clamp circuit comprising:

a first terminal;

a second terminal having a first voltage with respect to a voltage at the first terminal, such that the first terminal and the second terminal are coupled between an ESD protected circuit and a direct current (DC) reference;

a first enhancement-mode field effect transistor (FET) element formed using a compound semiconductor material and comprising;

a first drain coupled to the first terminal;

a first source coupled to the second terminal; and

a first gate;

a first resistive element coupled between the first gate and the second terminal, wherein when the first voltage exceeds a first threshold, the ESD clamp circuit is in a clamping state;

a plurality of enhancement-mode FET pseudomorphic high electron mobility transistor (pHEMT) elements;

comprising the first enhancement-mode FET element;

comprising a plurality of gates comprising the first gate; and

such that each of the plurality of enhancement-mode pHEMT elements is coupled in series to form a chain having the first drain at one end of the chain and a second source at another end of the chain, wherein the second source is coupled to the second terminal; and

a plurality of resistive elements comprising the first resistive element, such that each of the plurality of resistive elements is coupled between a corresponding each of the plurality of gates and the second terminal.

17. The ESD clamp circuit of claim 16 further comprising a series resistive element coupled between the first terminal and the first drain.

18. The ESD clamp circuit of claim 16 wherein the enhancement-mode FET is a enhancement-mode pseudomorphic high electron mobility transistor (pHEMT) element.

19. An electrostatic discharge (ESD) clamp circuit comprising:

a first terminal;

a second terminal having a first voltage with respect to a voltage at the first terminal, such that the first terminal and the second terminal are coupled between an ESD protected circuit and a direct current (DC) reference;

a first enhancement-mode field effect transistor (FET) element formed using a compound semiconductor material and comprising;

a first drain coupled to the first terminal;

a first source coupled to the second terminal; and

a first gate; and

a first resistive element coupled between the first gate and the second terminal, wherein when the first voltage exceeds a first threshold, the ESD clamp circuit is in a clamping state; and

wherein the ESD protected circuit is fed from a complementary metal oxide semiconductor (CMOS) controller power supply and the first terminal and the second terminal are coupled between the CMOS controller power supply and the DC reference.

20. An electrostatic discharge (ESD) clamp circuit comprising:

a first terminal;

a second terminal having a first voltage with respect to a voltage at the first terminal, such that the first terminal and the second terminal are coupled between an ESD protected circuit and a direct current (DC) reference;

a first enhancement-mode field effect transistor (FET) element formed using a compound semiconductor material and comprising;

a first drain coupled to the first terminal;

a first source coupled to the second terminal; and

a first gate;

a first resistive element coupled between the first gate and the second terminal, wherein when the first voltage exceeds a first threshold, the ESD clamp circuit is in a clamping state;

a plurality of enhancement-mode FET elements;

comprising the first enhancement-mode FET element;

a plurality of gates comprising the first gate; and

such that each of the plurality of enhancement-mode FET elements is coupled in series to form a chain having the first drain at one end of the chain and a second source at another end of the chain, wherein the second source is coupled to the second terminal; and

a plurality of resistive elements comprising the first resistive element, such that each of the plurality of resistive elements is coupled between a corresponding each of the plurality of gates and the second terminal.