Asymmetric write current compensation using gate overdrive for resistive sense memory cells
First Claim
1. An apparatus comprising:
- a resistive sense memory (RSM) cell comprising an RSM element coupled to a switching device, the switching device comprising a plurality of terminals; and
a control circuit which compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across said terminals to be equal to or less than a magnitude of a source voltage applied to the switching device to provide bi-directional write currents of substantially equal magnitude through the RSM element.
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Abstract
Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
74 Citations
20 Claims
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1. An apparatus comprising:
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a resistive sense memory (RSM) cell comprising an RSM element coupled to a switching device, the switching device comprising a plurality of terminals; and a control circuit which compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across said terminals to be equal to or less than a magnitude of a source voltage applied to the switching device to provide bi-directional write currents of substantially equal magnitude through the RSM element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
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providing a resistive sense memory (RSM) cell comprising an RSM element coupled to a switching device; and compensating for asymmetric write characteristics of the RSM cell by; pre-charging a first control line to a source voltage; and applying a first gate control voltage to the switching device to pass a first write current from the pre-charged first control line, through the switching device and to the RSM element to program a first resistive state, the first gate control voltage selected to be greater than the source voltage by a delta voltage value equal to a voltage drop across the RSM element. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A semiconductor memory comprising:
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an array of memory cells each comprising a resistive sense memory (RSM) element coupled to a switching device; and a control circuit adapted to apply bi-directional write currents of substantially equal magnitude through a selected memory cell of the array in a hard direction and an easy direction, respectively, the control circuit applying a first gate control voltage to a gate of the switching device greater than a source voltage in said hard direction, the control circuit applying a second gate control voltage to said gate equal to or less than the source voltage in said easy direction. - View Dependent Claims (19, 20)
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Specification