Clock and control signal generation for high performance memory devices
First Claim
1. An integrated circuit comprising:
- a first clock generator configured to generate a first clock signal used for memory read and memory write operations; and
a second clock generator configured to generate a second clock signal used for memory write operations and not used for memory read operations,wherein the second clock generator is disabled when memory read operations are performed; and
wherein the first clock generator comprises a first circuit configured to generate leading edges on the first clock signal based on an external clock signal and to generate trailing edges on the first clock signal based on a reset signal.
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Accused Products
Abstract
Techniques for generating clock and control signals to achieve good performance for read and write operations in memory devices are described. In one design, a clock and control signal generator within a memory device includes first and second clock generators, first and second control signal generators, and a reset circuit. The first clock generator generates a first clock signal used for read and write operations. The second clock generator generates a second clock signal used for write operations. The reset circuit generates at least one reset signal for the first and second clock generators. The reset signal(s) may have timing determined based on loading due to dummy cells. The first control signal generator generates control signals used for read and write operations based on the first clock signal. The second control signal generator generates control signals used for write operations based on the second clock signal.
20 Citations
30 Claims
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1. An integrated circuit comprising:
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a first clock generator configured to generate a first clock signal used for memory read and memory write operations; and a second clock generator configured to generate a second clock signal used for memory write operations and not used for memory read operations, wherein the second clock generator is disabled when memory read operations are performed; and wherein the first clock generator comprises a first circuit configured to generate leading edges on the first clock signal based on an external clock signal and to generate trailing edges on the first clock signal based on a reset signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15)
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12. An integrated circuit comprising:
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a first clock generator configured to generate a first clock signal used for memory read and memory write operations; a second clock generator configured to generate a second clock signal used for memory write operations and not used for memory read operations; a reset circuit configured to generate at least one reset signal for the first and second clock generators; and a memory array comprising memory cells and dummy cells, and wherein the reset circuit generates the at least one reset signal with timing determined based on loading on a bit line for a column of dummy cells in the memory array. - View Dependent Claims (13)
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16. An integrated circuit comprising:
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a first clock generator configured to generate a first clock signal used for memory read and memory write operations; a second clock generator configured to generate a second clock signal used for memory write operations and not used for memory read operations; a reset circuit configured to generate at least one reset signal for the first and second clock generators; and a power-on reset circuit configured to receive the first and second clock signals and generate a third clock signal for the reset circuit, the power-on reset circuit resetting the first and second clock signals to a known logic level at power on.
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17. A method comprising:
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generating a first clock signal used for memory read and memory write operations; and generating a second clock signal used for memory write operations and not used for memory read operations, the first and second clock signals having equal delays, wherein the generating a second clock signal step is disabled when memory read operations are performed; and wherein generating the first clock signal comprises generating leading edges on said first clock signal based on an external clock signal and generating trailing edges on said first clock signal based on a reset signal. - View Dependent Claims (19, 20)
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18. A method comprising:
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generating a first clock signal used for memory read and memory write operations; generating a second clock signal used for memory write operations and not used for memory read operations, the first and second clock signals having equal delays; and generating at least one reset signal having timing determined based on a plurality of dummy cells; and wherein said reset signal is for resetting the first and second clock signals.
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21. An apparatus comprising:
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means for generating a first clock signal used for memory read and memory write operations; and means for generating a second clock signal used for memory write operations and not used for memory read operations, the first and second clock signals having equal delays, wherein the means for generating a second clock signal is disabled when memory read operations are performed; and wherein the means for generating the first clock signal comprises a first circuit configured to generate leading edges on the first clock signal based on an external clock signal and to generate trailing edges on the first clock signal based on a reset signal. - View Dependent Claims (22, 23, 24)
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25. An integrated circuit comprising:
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a clock generator configured to generate a first clock signal used for memory read and memory write operations; a control signal generator configured to receive the first clock signal and generate a second clock signal used for memory write operations, the second clock signal being enabled only for memory write operations; and a reset circuit configured to generate a reset signal for the clock generator, the reset signal having timing determined based on loading due to a plurality of dummy cells. - View Dependent Claims (26)
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27. A computer-readable storage medium storing data, which, when executed by an integrated circuit, cause the integrated circuit to perform operational instructions, the instructions comprising:
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program code to enable a first clock generator to generate a first clock signal used for memory read and memory write operations; and program code to enable a second clock generator to generate a second clock signal used for memory write operations and not used for memory read operations; and wherein the first clock generator comprises a first circuit configured to generate leading edges on the first clock signal based on an external clock signal and to generate trailing edges on the first clock signal based on a reset signal.
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28. A method, comprising:
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generating a first clock signal used for memory read and memory write operations; generating, based on the first clock signal, a second clock signal used for memory write operations, the second clock signal being enabled only for memory write operations; and generating a reset signal for a clock generator that generates the first clock signal, the reset signal having timing determined based on loading due to a plurality of dummy cells.
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29. An integrated circuit, comprising:
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means for generating a first clock signal used for memory read and memory write operations; means for generating, based on the first clock signal, a second clock signal used for memory write operations, the second clock signal being enabled only for memory write operations; and means for generating a reset signal for the means for generating the first clock signal, the reset signal having timing determined based on loading due to a plurality of dummy cells.
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30. A computer-readable storage medium storing data, which, when executed by an integrated circuit, cause the integrated circuit to perform operational instructions, the instructions comprising:
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program code to enable a first clock generator to generate a first clock signal used for memory read and memory write operations; program code to enable a second clock generator to generate, based on the first clock signal, a second clock signal used for memory write operations, the second clock signal being enabled only for memory write operations; and program code to enable a reset circuit to generate a reset signal for the program code to enable the first clock generator to generate the first clock signal, the reset signal having timing determined based on loading due to a plurality of dummy cells.
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Specification