Circuit providing load isolation and memory domain translation for memory module

• US 7,881,150 B2
• Filed: 12/02/2009
• Issued: 02/01/2011
• Est. Priority Date: 03/05/2004
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Solomon, Jeffrey C., Bhakta, Jayesh R.
• Primary Examiner(s): Nguyen; Dang T
• Assistant Examiner(s): Sofocleous; Alexander
• Application Number:
  US12/629,827
• Publication Number:
  US 20100128507A1
• Time in Patent Office: 426 Days
• Field of Search: 365/51, 365/149, 365/230.03, 365/230.06, 365/233.13
• US Class Current: 365/233.13
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/10159 Memory
• CPC Class Codes: H05K 2203/1572 Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A circuit is configured to be mounted on a memory module so as to be electrically coupled to a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks on the memory module. The circuit includes a logic element, a register, and a phase-lock loop device. The circuit is configurable to respond to a set of input signals from a computer system to selectively isolate one or more loads of the plurality of DDR memory devices from the computer system and to translate between a system memory domain of the computer system and a physical memory domain of the plurality of DDR memory devices.

Claims

1. A circuit configured to be mounted on a memory module so as to be electrically coupled to a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks on the memory module, the memory module configured to be electrically coupled to a memory controller of a computer system so as to receive a set of input signals, comprising row address signals, column address signals, bank address signals, and chip-select signals, the set of input signals compatible with a system memory domain of the computer system, the circuit comprising:

a logic element;

a register;

a phase-lock loop device configured to be operationally coupled to the plurality of DDR memory devices, the logic element, and the register,

wherein the circuit is configurable to be responsive to the set of input signals by selectively isolating one or more loads of the DDR memory devices from the computer system, the circuit configurable to translate between the system memory domain of the computer system and a physical memory domain of the plurality of DDR memory devices, wherein the system memory domain has a first memory density per rank and the physical memory domain has a second memory density per rank less than the first memory density per rank.

2. The circuit of claim 1, wherein the plurality of DDR memory devices has a first number of DDR memory devices, and the circuit is configurable to selectively isolate the loads of a second number of the DDR memory devices from the computer system, the second number less than the first number.

3. The circuit of claim 2, wherein the circuit is configurable to selectively isolate the loads of the second number of the DDR memory devices from the computer system in response to a command or address signal of the set of input signals.

4. The circuit of claim 1, wherein the system memory domain is compatible with a first number of chip-select signals, and the physical memory domain is compatible with a second number of chip-select signals greater than the first number of chip-select signals.

5. The circuit of claim 1, wherein two or more of the phase-lock loop device, the logic element, and the register are portions of a single component.

6. The circuit of claim 1, wherein the circuit is configurable to transmit a set of output signals to the plurality of DDR memory devices, the set of output signals compatible with the physical memory domain.

7. The circuit of claim 6, wherein the circuit is configurable to receive a command signal from the computer system, select at least one rank of the one or more ranks, and transmit the command signal to at least one DDR memory device of the selected rank of DDR memory devices.

8. The circuit of claim 6, wherein the set of input signals comprises a first set of address and command signals and the set of output signals comprises a second set of address and command signals.

9. The circuit of claim 8, wherein the circuit is configurable to store an address signal of the set of input signals during a row access procedure and pass the stored address signal as an address signal of the set of output signals during a subsequent column address procedure.

10. The circuit of claim 1, further configurable to selectively isolate a data signal line of a DDR memory device of the plurality of DDR memory devices from the computer system.

11. The circuit of claim 1, further configurable to receive an address signal of the set of input signals and to use the address signal to translate between the system memory domain and the physical memory domain.

12. The circuit of claim 11, wherein the address signal is a row address bit and the circuit is configurable to latch the row address bit.

13. The circuit of claim 11, wherein the address signal is a row address bit and the circuit is configurable to use the row address bit and a first number of chip-select signals of the set of input signals to generate a second number of chip-select signals greater than the first number of chip-select signals.

14. The circuit of claim 11, wherein the address signal is a row address bit and the circuit is configurable to use the row address bit and a first number of column address strobe (CAS) signals to generate a second number of CAS signals greater than the first number of CAS signals.

15. A circuit configured to be mounted on a memory module so as to be electrically coupled to a first double-data-rate (DDR) memory device having a first data signal line and a first data strobe line, to a second DDR memory device having a second data signal line and a second data strobe line, and to a common data signal line, the memory module configured to be electrically coupled to a memory controller of a computer system so as to receive a set of input signals comprising row address signals, column address signals, bank address signals, and chip-select signals, the set of input signals compatible with a system memory domain of the computer system, the circuit comprising:

a logic element;

a register;

a phase-lock loop device configured to be operationally coupled to the first DDR memory device, the second DDR memory device, the logic element, and the register,

wherein the circuit is configurable to be responsive to the set of input signals by selectively electrically coupling the first data signal line to the common data signal line and selectively electrically coupling the second data signal line to the common data signal line, the circuit configurable to translate between the system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain has a first memory density per memory device, and the physical memory domain has a second memory density per memory device less than the first memory density per memory device.

16. The circuit of claim 15, wherein the two or more of the logic element, the register, and the phase-lock loop device are portions of a single component.

17. The circuit of claim 16, further comprising one or more switches selectively electrically coupling the first data signal line to the common data signal line and selectively electrically coupling the second data signal line to the common data signal line, the one or more switches operatively coupled to the logic element to receive control signals from the logic element.

18. The circuit of claim 15, wherein the memory module further comprises a third data strobe signal line connectable to the computer system, the circuit electrically coupled to the first data strobe signal line, to the second data strobe signal line, and to the third data strobe signal line, the circuit configurable to selectively electrically couple the first data strobe signal line to the third data strobe signal line and to selectively electrically couple the second data strobe signal line to the third data strobe signal line.

19. The circuit of claim 15, wherein the circuit is configurable to save an address signal of the set of input signals during a row access procedure and pass the saved address signal as an address signal during a subsequent column address procedure.

20. The circuit of claim 15, further configurable to be responsive to the set of input signals by selectively electrically coupling both the first data signal line and the second data signal line to the computer system.

21. The circuit of claim 15, wherein the circuit is configurable to selectively isolate both the first data signal line and the second data signal line from the computer system.

22. A circuit configured to be mounted on a memory module so as to be electrically coupled to a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks on the memory module, the memory module configured to be electrically coupled to a memory controller of a computer system so as to receive a set of input signals, comprising row address signals, column address signals, bank address signals, and chip-select signals, the set of input signals compatible with a system memory domain of the computer system, the circuit comprising:

a logic element;

a register;

a phase-lock loop device configured to be operationally coupled to the plurality of DDR memory devices, the logic element, and the register,

wherein the circuit is configurable to be responsive to the set of input signals by selectively isolating one or more loads of the DDR memory devices from the computer system, the circuit configurable to translate between the system memory domain of the computer system and a physical memory domain of the plurality of DDR memory devices, wherein the system memory domain is compatible with a first number of chip-select signals, and the physical memory domain is compatible with a second number of chip-select signals greater than the first number of chip-select signals.

23. The circuit of claim 22, wherein the plurality of DDR memory devices has a first number of DDR memory devices, and the circuit is configurable to selectively isolate the loads of a second number of the DDR memory devices from the computer system, the second number less than the first number.

24. The circuit of claim 22, wherein two or more of the logic element, the register, and the phase-lock loop device are portions of a single component.

25. The circuit of claim 22, wherein the circuit is configurable to store an address signal of the set of input signals during a row access procedure and to pass the stored address signal during a subsequent column address procedure.

26. The circuit of claim 22, further configurable to selectively isolate a data signal line of a DDR memory device of the plurality of DDR memory devices from the computer system.

27. The circuit of claim 22, further configurable to receive an address signal of the set of input signals and to use the address signal to translate between the system memory domain and the physical memory domain.

28. The circuit of claim 27, wherein the address signal is a row address bit and the circuit is configurable to latch the row address bit.

29. The circuit of claim 27, wherein the address signal is a row address bit and the circuit is configurable to use the row address bit and the first number of chip-select signals to generate the second number of chip-select signals.

30. The circuit of claim 27, wherein the address signal is a row address bit and the circuit is configurable to use the row address bit and a first number of column address strobe (CAS) signals to generate a second number of CAS signals greater than the first number of CAS signals.

31. A circuit configured to be mounted on a memory module so as to be electrically coupled to a first double-data-rate (DDR) memory device having a first data signal line and a first data strobe line, to a second DDR memory device having a second data signal line and a second data strobe line, and to a common data signal line, the memory module configured to be electrically coupled to a memory controller of a computer system so as to receive a set of input signals comprising row address signals, column address signals, bank address signals, and chip-select signals, the set of input signals compatible with a system memory domain of the computer system, the circuit comprising:

a logic element;

a register;

a phase-lock loop device configured to be operationally coupled to the first DDR memory device, the second DDR memory device, the logic element, and the register,

wherein the circuit is configurable to be responsive to the set of input signals by selectively electrically coupling the first data signal line to the common data signal line and selectively electrically coupling the second data signal line to the common data signal line, the circuit configurable to translate between the system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain is compatible with a first number of chip-select signals, and the physical memory domain is compatible with a second number of chip-select signals greater than the first number of chip-select signals.

32. The circuit of claim 31, wherein two or more of the logic element, the register, and the phase-lock loop device are portions of a single component.

33. The circuit of claim 31, further comprising one or more switches configurable to selectively electrically couple the first data signal line to the common data signal line and to selectively electrically couple the second data signal line to the common data signal line, the one or more switches operatively coupled to the logic element to receive control signals from the logic element.

34. The circuit of claim 31, wherein the circuit is configurable to save an address signal of the set of input signals during a row access procedure and to pass the saved address signal as an address signal during a subsequent column address procedure.

35. The circuit of claim 31, further configurable to be responsive to the set of input signals by selectively electrically coupling both the first data signal line and the second data signal line to the computer system.

36. The circuit of claim 31, further configurable to selectively isolate both the first data signal line and the second data signal line from the computer system.