Configurable ports for a host ethernet adapter
First Claim
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1. An Ethernet adapter comprising:
- a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor;
wherein the plurality of layers include in one layer a plurality of media access controllers (MACs) and a high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to different speed data sources on the same pins;
wherein each of the plurality of MACs includes its own physical coding unit for aligning and coding the transmit packets, wherein the high speed serdes can be configured in different modes of operation by setting different frequency multiplication ratios;
wherein the frequency of the reference clock is relatively low compared to the data sources because a phase locked loop (PLL) is adjustable to different frequency multiplication ratios to allow the different data sources.
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Abstract
A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
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Citations
17 Claims
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1. An Ethernet adapter comprising:
a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor;
wherein the plurality of layers include in one layer a plurality of media access controllers (MACs) and a high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to different speed data sources on the same pins;
wherein each of the plurality of MACs includes its own physical coding unit for aligning and coding the transmit packets, wherein the high speed serdes can be configured in different modes of operation by setting different frequency multiplication ratios;
wherein the frequency of the reference clock is relatively low compared to the data sources because a phase locked loop (PLL) is adjustable to different frequency multiplication ratios to allow the different data sources.- View Dependent Claims (2, 3, 4, 5, 6)
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7. A network interface controller (NIC) comprising:
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an interface to a private bus; and an Ethernet adapter coupled to the interface;
the Ethernet adapter comprising a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor;
wherein the plurality of layers include in one layer a plurality of media access controllers (MACs) and a high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to different speed data sources on the same pins;
wherein each of the plurality of MACs includes its own physical coding unit for aligning and coding the transmit packets;
wherein the high speed serdes can be configured in different modes of operation by setting different frequency multiplication ratios;
wherein the frequency of the reference clock is relatively low compared to the data sources because a phase locked loop (PLL) is adjustable to different frequency multiplication ratios to allow the different data sources. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A network interface controller (NIC) comprising:
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an interface coupled to a private bus; and an Ethernet adapter coupled to the interface, a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor via the private bus, wherein the plurality of layers include in one layer a plurality of media access controllers (MACs) and a high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to a 10 Gigabit (G) source and a plurality of 1 G sources on the same pins, wherein each of the plurality of MACs includes its own physical coding unit for aligning and coding the transmit packets, wherein the high speed serdes can be configured in different modes of operation by setting different frequency multiplication ratios;
wherein the frequency of the reference clock is relative low compared to the data sources because a phase locked loop (PLL) is adjustable to different frequency multiplication ratios to allow the different data sources. - View Dependent Claims (14, 15, 16)
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17. A server comprising:
- a processor;
the processor including a private bus; and
a network interface controller (NIC) coupled to the private bus, the NIC including an Ethernet adapter;
the Ethernet adapter comprising a plurality of layers for allowing the adapter to receive and transmit packets from and to the processor;
wherein the plurality of layers include in one layer a plurality of media access controllers (MACs) and a high speed serializer/deserializer (high speed serdes) to receive data from and provide data to different speed data sources on the same pins;
wherein each of the plurality of MACs includes its own physical coding unit for aligning and coding the transmit packets, wherein the high speed serdes can be configured in different modes of operation by setting different frequency multiplication ratios;
wherein the frequency of the reference clock is relatively low compared to the data sources because a phase locked loop (PLL) is adjustable to different frequency multiplication ratios to allow the different data sources.
- a processor;
Specification