Methods of calibrating a clock using multiple clock periods with a single counter and related devices and methods
First Claim
1. A method of calibrating a first clock signal using a second clock signal and a plurality of calibration periods, the method comprising:
- generating incremented counter values at a counter responsive to edges of the second clock signal;
for each of the plurality of calibration periods, storing in memory an initial incremented counter value from the counter at an initial edge of the first clock signal for the respective calibration period and storing in the memory a final incremented counter value from the counter at a final edge of the first clock signal for the respective calibration period wherein at least two of the plurality of calibration periods are overlapping with different initial and final edges of the first clock signal;
for each of the plurality of calibration periods, determining a number of edges of the second clock signal occurring during the respective calibration period using the initial and final incremented counter values stored in the memory; and
determining a relationship between the first and second clock signals using a sum of a number of edges of the second clock signal occurring during each of the plurality of calibration periods and using a sum of a number of first clock signal cycles occurring during each of the plurality of calibration periods.
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Accused Products
Abstract
A method of calibrating a first clock signal using a second clock signal and a plurality of calibration periods may include generating incremented counter values at a counter responsive to edges of the second clock signal. For at least two of the plurality of calibration periods, an initial incremented counter value from the counter may be stored in memory at an initial edge of the first clock signal for the respective calibration period, a final incremented counter value may be stored in memory at a final edge of the clock signal for the respective calibration period, and the at least two of the plurality of calibration periods may be overlapping with different initial and final edges of the first clock signal. For each of the plurality of calibration periods, a number of edges of the second clock signal occurring during the respective calibration period may be determined using the initial and final incremented counter values stored in memory. A relationship between the first and second clock signals may be determined using a sum of a number of edges of the second clock signal occurring during each of the plurality of calibration periods and using a sum of a number of first clock signal cycles occurring during each of the plurality of calibration periods.
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Citations
17 Claims
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1. A method of calibrating a first clock signal using a second clock signal and a plurality of calibration periods, the method comprising:
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generating incremented counter values at a counter responsive to edges of the second clock signal; for each of the plurality of calibration periods, storing in memory an initial incremented counter value from the counter at an initial edge of the first clock signal for the respective calibration period and storing in the memory a final incremented counter value from the counter at a final edge of the first clock signal for the respective calibration period wherein at least two of the plurality of calibration periods are overlapping with different initial and final edges of the first clock signal; for each of the plurality of calibration periods, determining a number of edges of the second clock signal occurring during the respective calibration period using the initial and final incremented counter values stored in the memory; and determining a relationship between the first and second clock signals using a sum of a number of edges of the second clock signal occurring during each of the plurality of calibration periods and using a sum of a number of first clock signal cycles occurring during each of the plurality of calibration periods. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A mobile device comprising:
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a first clock signal generator configured to generate a first clock signal; a second clock signal generator configured to generate a second clock signal; a counter coupled to the second clock signal generator wherein the counter is configured to generate incremented counter values at a counter responsive to edges of the second clock signal; memory coupled to the counter wherein the memory is configured for each of a plurality of calibration periods to store an initial incremented counter value from the counter at an initial edge of the first clock signal for the respective calibration period and to store a final incremented counter value from the counter at a final edge of the first clock signal for the respective calibration period wherein at least two of the plurality of calibration periods are overlapping with different initial and final edges of the first clock signal; and a processor coupled to the memory wherein for each of the plurality of calibration periods the processor is configured to determine a number of edges of the second clock signal occurring during the respective calibration period using the initial and final incremented counter values, and wherein the processor is configured to determine a relationship between the first and second clock signals using a sum of a number of edges of the second clock signal occurring during each of the plurality of calibration periods and using a sum of a number of first clock signal cycles occurring during each of the plurality of calibration periods. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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Specification