Processor, data transfer unit, multicore processor system

• US 7,882,277 B2
• Filed: 07/14/2008
• Issued: 02/01/2011
• Est. Priority Date: 08/29/2007
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Todaka, Takashi
• Primary Examiner(s): Shin; Christopher B
• Application Number:
  US12/172,891
• Publication Number:
  US 20090063812A1
• Time in Patent Office: 932 Days
• Field of Search: 710 5- 6, 710 15- 19, 710 22- 24, 710 33- 34, 710/58, 714 15- 21
• US Class Current: 710/24
• CPC Class Codes: G06F 11/1443 Transmit or communication errors

Abstract

A processor includes a CPU capable of performing predetermined arithmetic processing, a memory accessible by the CPU, and a data transfer unit capable of controlling data transfer with the memory by substituting for the CPU. The data transfer unit is provided with a command chain unit for continuously performing data transfer by execution of a preset command chain, and a retry controller for executing a retry processing in case a transfer error occurs during data transfer by the command chain unit. Then, the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain, thereby lessening the number of interruptions for error processing, and attaining enhancement in performance of a system.

Claims

1. A multicore processor system comprising a plurality of processor cores, each capable of performing predetermined arithmetic and logical processing, and a common memory shared by the plurality of the processor cores,

wherein the processor core includes:

a CPU capable of performing predetermined arithmetic and logical processing;

a core internal memory accessible by the CPU; and

a data transfer unit capable of controlling data transfer between the core internal memory and the common memory, by substituting for the CPU,

the data transfer unit includes;

a command chain unit for continuously performing data transfer by execution of a preset command chain; and

a retry controller for performing a retry-processing in case a transfer error occurs during data transfer by the command chain unit,

wherein the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain.

2. The multicore processor system according to claim 1, wherein the number of retries at the retry controller is set for every command in the command chain.

3. The multicore processor system according to claim 1, wherein if the transfer error cannot be avoided by the retry, the retry controller is capable of causing the command chain unit to skip the command relating to the transfer error to thereby execute a command succeeding thereto.

4. The multicore processor system according to claim 1, wherein the retry controller includes a storage area capable of sequentially storing commands relating to the transfer error, and the commands stored in the storage area are reported all together to the CPU after completion of the command chain.