Processor performance adjustment system and method

• US 7,882,369 B1
• Filed: 11/14/2002
• Issued: 02/01/2011
• Est. Priority Date: 11/14/2002
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Lam, John, Kelleher, Brian M., Kranzusch, Kevin, Mimberg, Ludger, Velmurugan, Senthil S.
• Primary Examiner(s): Bae; Ji H.
• Application Number:
  US10/295,619
• Time in Patent Office: 3,001 Days
• Field of Search: 713/300, 713/320, 713/322, 345/419
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention performance enhancement and reliability maintenance system and method pushes a processor to its maximized performance capabilities when performing processing intensive tasks (e.g., 3D graphics, etc). For example, a clock speed and voltage are increased until an unacceptable error rate begins to appear in the processing results and then the clock speed and voltage are backed off to the last setting at which excessive errors did not occur, enabling a processor at its full performance potential. The present invention also includes the ability to throttle back settings which facilitates the maintenance of desired reliability standards. The present invention is readily expandable to provide adjustment for a variety of characteristics in response to task performance requirements. For example, a variable speed fan that is software controlled can be adjusted to alter the temperature of the processor in addition to clock frequency and voltage.

Claims

1. A processor adjustment system comprising:

a processing unit for performing tasks;

a voltage source unit for generating a power signal for said processing unit;

a performance testing component for testing the performance of said processing unit to determine a high voltage level and a low voltage level at which said processing unit begins to fail;

a voltage control component for controlling the voltage level of said power signal within an envelope determined by said performance testing component, wherein said power signal voltage is increased for high performance tasks and reduced for low performance tasks of said processing unit, wherein said high performance tasks comprise rendering three-dimensional graphics images; and

a memory for storing test suite instructions for execution by said performance testing component.

2. The processor adjustment system of claim 1 further comprising:

a clock signal generating unit for generating a clock signal for said processing unit; and

a clock control component for controlling the frequency of said clock signal within an envelope determined by said performance testing component, wherein said clock signal frequency is increased for high performance tasks and reduced for low performance tasks of said processing unit.

3. The processor adjustment system of claim 1 wherein said processing unit is a graphics processor.

4. The processor adjustment system of claim 1 wherein said testing is performed at each power up of said system.

5. The processor adjustment system of claim 1 wherein the performance nature of said task is user defined.

6. The processor adjustment system of claim 1 wherein the performance nature of said task is defined by an application program executing said task.

7. The processor adjustment system of claim 1 wherein said testing is performed periodically.

8. A processor adjustment system comprising:

a processing unit for performing processing tasks;

a clock signal generating unit for generating a clock signal for said processing unit;

a performance testing component for periodically testing the performance of said processing unit to determine an envelope including a high clock frequency and a low clock frequency at which said processing unit begins to fail;

a clock control component for controlling the frequency of said clock signal within said envelope determined by said performance testing component, wherein said clock signal frequency is increased for high performance tasks and reduced for low performance tasks of said processing unit, wherein said high performance tasks comprise rendering three-dimensional graphics images; and

a memory for storing test suite instructions for execution by said performance testing component.

9. The processor adjustment system of claim 8 wherein said performance testing component also determines a minimum clock frequency at which said processing unit begins to fail.

10. The processor adjustment system of claim 8 wherein said performance testing component is controlled by software running on a CPU, said CPU being different from said processing unit.

11. The processor adjustment system of claim 8 further comprising a voltage control component for controlling the voltage level of a power signal for said processing unit, wherein said power signal voltage is set to a higher voltage for said high performance tasks than for said low performance tasks.

12. The processor adjustment system of claim 8 wherein said processor is a graphics processor.

13. The processor adjustment system of claim 12 wherein said high performance tasks comprise rendering interactive three-dimensional graphics images.

14. The processor adjustment system of claim 13 wherein said low performance tasks do not comprise rendering interactive three-dimensional graphics images.

15. A processor adjustment system of claim 8 wherein said test suite instructions and models are included in a basic input output system (BIOS).

16. A processor adjustment system of claim 15 wherein said test suite instructions are based upon binning of said processor unit and said memory on an individual and combined board basis.

17. A processor adjustment system of claim 16 wherein said test suite instructions are changed in response to results of a self test operation.

18. A processor performance enhancement and reliability balancing method comprising:

storing test suite instructions in a memory for execution by a performance testing component;

testing processor performance, wherein said testing comprises determining a high clock frequency and a low clock frequency at which said processor begins to fail;

making an adjustment to reduce a failure rate;

determining if said processor is engaged in a high performance task, wherein said high performance tasks comprise rendering three-dimensional graphics images;

adjusting operating condition settings for a high performance task, including increasing the speed of a fan during said high performance task;

determining if said processor is engaged in a low performance task; and

adjusting operating condition setting for a low performance task, including decreasing the speed of a fan during said low performance task.

19. The processor performance enhancement and reliability balancing method of claim 18 wherein said testing provides an indication of errors.

20. The processor performance enhancement and reliability balancing method of claim 19 wherein said indication of an error occurring does not trigger an operating condition adjustment unless a predetermined unacceptable level of errors occur.

21. The processor performance enhancement and reliability balancing method of claim 20 wherein crossing a threshold triggers tests that determine said adjustment to said operating condition.

22. The processor performance enhancement and reliability balancing method of claim 19 wherein said indication of a single error triggers an operating condition adjustment.

23. The processor performance enhancement and reliability balancing method of claim 22 wherein crossing a threshold triggers tests that determine said adjustment to said operating condition.

24. The processor performance enhancement and reliability balancing method of claim 19 wherein the type of error is considered in addition to the number of errors before making an operating condition adjustment.

25. The processor performance enhancement and reliability balancing method of claim 18 wherein said testing further comprises determining a high voltage and a low voltage at which said processor begins to fail.

26. The processor performance enhancement and reliability balancing method of claim 18 further comprising adjusting the clock frequency of said processor if said processor passes said testing.

27. The processor performance enhancement and reliability balancing method of claim 18 further comprising increasing the speed of a fan during a high performance task.

28. The processor performance enhancement and reliability balancing method of claim 18 wherein said processor is a graphics processor.

29. A processor performance limitation testing method comprising:

adjusting the voltage level of a power supply signal supplied to a processor;

altering the frequency of a clock signal that clocks said processor;

determining combinations of voltage level values of said power signal and frequency values of said clock signal at which said processor begins to fail, said determining further comprising determining a high voltage and clock frequency and a low voltage and clock frequency at which said processor begins to fail;

wherein said determining includes running a hardware self test and factoring results of said hardware self test into said determining combinations of voltage level values of said power signal and frequency values for different performance task, wherein a high performance task comprises rendering three-dimensional graphics images.

30. The processor performance limitation testing method of claim 29 further comprising altering the temperature of said processor.

31. The processor performance limitation testing method of claim 29 wherein said frequency is increased for high performance tasks and reduced for low performance tasks of said processing unit, wherein said high performance tasks comprise rendering interactive three-dimensional graphics images.

32. The processor performance limitation testing method of claim 29 wherein said processor is a graphics processor.

33. A computer system comprising:

a CPU;

a memory coupled to said CPU for storing test suite instructions for execution by a performance testing component;

a graphics processing unit for performing processing tasks;

a control unit coupled to said CPU for controlling a clock signal and a power signal for said graphics processing unit, wherein the frequency of said clock signal and voltage level of said power signal is adjusted based upon user demanded performance, said user demanded performance including a high performance task comprising rendering three-dimensional graphics images; and

wherein said control unit maintains said frequency of said clock signal and said voltage level of said power signal within an envelope determined by said control unit, wherein limitations of said envelope are defined by a high voltage and clock frequency and a low voltage and clock frequency at which said processor begins to produce errors at an unacceptable rate.

34. A computer system of claim 33 wherein limitations of said envelope are defined by a point at which said processor begins to produce errors at an unacceptable rate.

35. A computer system of claim 34 wherein said control unit also controls fan operations directed to maintaining the temperature of said processor within an acceptable range.

36. A processor management method comprising:

storing test suite instructions in a memory for execution by a performance testing component;

selecting a desired processor management objective, wherein said management objective is associated with a particular application type of task;

analyzing an operating condition of a processor, wherein said analyzing comprises executing said test suite instructions to determine a high clock frequency and voltage and a low clock frequency and voltage at which the processor begins to fail;

comparing said operating condition of said processor to an operating condition setting associated with said desired management objective; and

adjusting said operating condition of said processor according to said desired processor management objective, wherein said task comprises a high performance task comprising rendering three dimensional graphics images.

37. A processor management method of claim 36 wherein said management objective includes obtaining maximum performance with accurate results for a said particular application type of task.

38. A processor management method of claim 36 wherein said management objective includes conserving lifetime operating reliability of the processor while providing accurate results for an application type of task.

39. A processor management method of claim 36 wherein said management objective includes maintenance of a relatively low processor temperature.

40. A processor management method of claim 36 wherein said analyzing includes an examination of processor performance.

41. A processor management method of claim 36 wherein said analyzing includes determining the complexity of the task the processor is performing, the speed at which it is performing the task and the accuracy of the results.

42. A processor management method of claim 36 wherein a desired speed is indicated to be the maximum speed at which the processor can operate without introduction of an excessive error rate.

43. A processor management method of claim 36 wherein the frequency of a clock signal and voltage level of a power signal are adjusted.

44. A processor management method of claim 36 wherein the magnitude and direction of the frequency and voltage adjustment corresponds to said desired objective.

45. A processor management method of claim 36 wherein said desired objective is to obtain maximum performance with accurate results for particular application task and a clock signal frequency and a power signal voltage level are increased to a point just before errors begin to occur.

46. A processor management method of claim 36 wherein said desired objective is to conserve lifetime operating reliability of the processor during a low performance application task and a clock signal frequency and a power signal voltage level are reduced to a point just before errors begin to occur.

47. A processor management method of claim 36 wherein a temperature operating condition of the processor is altered.

48. A processor management method of claim 36 wherein a temperature operating condition of a processor is altered by changing a clock signal frequency, generating an interrupt that causes software to take additional actions, or directing a fan to provide more or less cooling.

49. A processor management method of claim 36 further comprising setting operating conditions to achieve multiple objectives with varying priorities.

50. A processor management method of claim 49 wherein said adjusting said operating condition of said processor is not performed unless a predetermined unacceptable level of errors occur.

51. A processor management method of claim 50 wherein crossing a threshold triggers tests that determine adjustments to said operating condition.

52. A processor management method of claim 49 wherein said adjusting said operating condition of said processor is performed in response to a single error detection.

53. A processor management method of claim 52 wherein crossing a threshold triggers tests that determine adjustments to said operating condition.

54. A processor management method of claim 49 wherein said analyzing comprises analysis of error indications.

55. A processor management method of claim 54 wherein the type of error is considered in addition to the number of errors before making an operating condition adjustment.

56. A processor management method of claim 36 wherein said processor is a graphics processor.

57. A processor adjustment system comprising:

a processor for processing information;

a means for storing test suite instructions for execution by a performance testing component;

a means for testing the performance of said processor, wherein said means for testing the performance of said processor determines a high clock signal frequency and power signal voltage level and a low clock signal frequency and power signal voltage level at which said processor begins to produce errors;

wherein said means for testing the performance of said processor determines whether the processor is performing a high performance task or a low performance task, said high performance task comprising rendering three dimensional graphics images; and

a means for adjusting multiple operating conditions of said processor based upon performance test results of said processor.

58. A processor adjustment system of claim 57 wherein said means for testing the performance of said processor comprises a set of error checking circuits distributed at various points within a graphics processing pipeline logic.

59. A processor adjustment system of claim 57 wherein said processor is a graphics processing unit and said means for testing the performance of said processor comprises software running on a central processing unit.

60. A processor adjustment system of claim 57 wherein said processor is a graphics processing unit and said means for testing the performance of said processor comprises software running within said graphics processing unit.

61. A processor adjustment system of claim 57 wherein said processor is a graphics processing unit and said means for testing the performance of said processor comprises external circuits that check outputs from said graphics processor unit.

62. The processor adjustment system of claim 57 wherein said operating conditions include a clock signal frequency and a power signal voltage level.

63. The processor adjustment system of claim 57 wherein said operating conditions include a temperature of said processor.

64. The processor adjustment system of claim 57 wherein said means for testing the performance of said processor determines clock signal frequencies and power signal voltage levels at which said processor begins to produce errors.

65. The processor adjustment system of claim 57 wherein said means for testing the performance of said processor determines whether a processor is performing a high performance or low performance task.

66. A computer system comprising:

a memory for storing test suite instructions for execution by a performance testing component;

a graphics processing unit for processing information and clocked by a clock signal frequency;

a temperature sensor for sensing temperature of said graphics processing unit;

a processor management component for controlling adjustments to operating conditions of said graphics processing unit, wherein said adjustments correspond to a combination of enhanced performance, particular application type of task, and reliability maintenance objectives for said graphics processing unit, wherein said task comprises a high performance task comprising rendering three dimensional graphics images; and

wherein said performance testing component determines a high clock frequency and voltage and a low clock frequency and voltage at which the processor begins to fail.

67. The computer system of claim 66 wherein said processor management component determine control adjustments of a clock signal frequency, a power signal voltage level supplied to said graphics processing unit and the operation of a fan for cooling said graphics processing unit.

68. The computer system of claim 66 wherein said adjustments correspond to a quiet mode operation.