Unidirectional error code transfer for both read and write data transmitted via bidirectional data link

• US 7,882,423 B2
• Filed: 06/05/2009
• Issued: 02/01/2011
• Est. Priority Date: 01/11/2006
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Wang, Yuanlong, Ware, Frederick A.
• Primary Examiner(s): Chase; Shelly A
• Application Number:
  US12/479,684
• Publication Number:
  US 20090249139A1
• Time in Patent Office: 606 Days
• Field of Search: 714/746, 714/763, 714/799, 714/758, 714/769
• US Class Current: 714/799
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 13/4286 using a handshaking protocol, e.g. RS232C link
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/611 Specific encoding aspects, e.g. encoding by means of decoding
• CPC Class Codes: H04L 1/0003 by switching between different modulation schemes
• CPC Class Codes: H04L 1/0008 : by supplementing frame payload, e.g. with padding bits
• CPC Class Codes: H04L 1/0061 : Error detection codes
• CPC Class Codes: H04L 1/08 : by repeating transmission, e.g. Verdan system H04L1/1858 and H04L1/189 take precedence
• CPC Class Codes: H04L 1/1867 : Arrangements specially adapted for the transmitter end
• CPC Class Codes: H04L 2001/0093 : Point-to-multipoint

Abstract

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Claims

1. A method of detecting error in memory communications over a signal link having a first end and an opposing end, comprising:

transmitting first data, including;

dynamically generating error-detection information for the first data at the first end,

transmitting the first data from the first end to the opposing end,

dynamically generating error-detection information for the first data at the opposing end, and

transmitting the error-detection information for the first data from the opposing end to the first end;

transmitting second data, including;

dynamically generating error-detection information for the second data at the opposing end,

transmitting the error-detection information for the second data from the opposing end to the first end,

transmitting the second data from the opposing end to the first end, and

dynamically generating error-detection information for the second data at the first end; and

at the first end, detecting errors based on error-detection information from the first end and error-detection information from the opposing end for the first data and for the second data.

2. The method of claim 1, wherein the first end is a controller end and the opposing end is a memory device end, the first data is write data and the second data is read data, including:

at the controller end, detecting errors based on error-detection information from the controller end and error-detection information from the memory device end for the write data and for the read data.

3. The method of claim 2, further comprising, for the write data, upon receipt of error detection information from the memory device end, retrieving reciprocal error detection information from the controller end to detect a mismatch.

4. The method of claim 1, further comprising performing a remedial retry action upon detection of a mismatch between error-detection information from the first end with corresponding error-detection information from the opposing end.

5. A memory device, comprising:

a receiver to receive write data from a data bus, the write data from a remote device;

a transmitter to send read data over the data bus to the remote device; and

logic to dynamically generate error detection information for each of the write data and the read data and to cause transmission of the error detection information for each of write data and read data to the remote device.

6. The memory device of claim 5, further comprising a group error computation mechanism that generates error-detection information for data in multiple memory transactions, the data including at least one of multiple read data and at least one of multiple write data.

7. A method of operating a memory device, comprising:

generating read error detection information in connection with data read operations, and sending the read error detection information to a memory controller;

generating write error detection information in connection with data write operations, and sending the write error detection information to the memory controller; and

correcting an error by prompting a remedial retry action using error detection information sent to the memory controller, with error correction being performed substantially only at the memory controller.

8. A method of operating a device, comprising:

receiving write mask information;

receiving first error-detection information corresponding to at least a portion of the write mask information;

dynamically generating second error-detection information for at least the portion of the write mask information; and

detecting errors in at least the portion of the write mask information based on the first error-detection information and the second error-detection information, and, if an error is detected, disabling a write operation to a memory core.

9. A controller comprising:

a transmitter circuit to transmit first data to a remote device;

an encoder to dynamically generate first error-detection information for the first data;

a receiver to receive from the remote device second error-detection information for the first data;

the receiver to receive from the remote device second data and first error-detection information for the second data;

the encoder to dynamically generate second error-detection information for the second data;

error detection circuits to detect errors based on the received error-detection information from the remote device and the generated error-detection information at the controller for the first and second data.

10. The controller of claim 9, wherein the remote device is a memory device, the first data is write data and the second data is read data, and wherein the error detection circuits detect errors based on the received error-detection information from the memory device and the generated error-detection information at the controller for the write data and for the read data.

11. The controller of claim 10, wherein the error detection circuits, upon receiving from the memory device error-detection information for the write data, retrieve the generated error detection information for the write data to detect a mismatch.

12. The controller of claim 9, further comprising a retry logic circuit to perform a remedial retry action upon detection of a mismatch between the generated error-detection information at the controller with the received error-detection information from the remote device.