Sequential equivalence checking for asynchronous verification
First Claim
1. A method, in a data processing system, for performing asynchronous verification of an integrated circuit design, comprising:
- receiving a first model of the integrated circuit design;
unfolding paths within the first model that have asynchronous crossings to generate an unfolded integrated circuit design model;
inserting asynchronous crossing logic into the unfolded integrated circuit design model to generate a second model;
correlating outputs of the first model with outputs of the second model;
applying one or more exclusive OR operations to the correlated outputs of the first model and the second model; and
performing, by the data processing system, sequential equivalence checking on the first model and second model utilizing the applied one or more exclusive OR operations, wherein the asynchronous crossing logic comprises skewing logic for selecting a phase difference between clocks of asynchronous domains of asynchronous crossings in the unfolded integrated circuit design.
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Abstract
Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.
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Citations
21 Claims
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1. A method, in a data processing system, for performing asynchronous verification of an integrated circuit design, comprising:
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receiving a first model of the integrated circuit design; unfolding paths within the first model that have asynchronous crossings to generate an unfolded integrated circuit design model; inserting asynchronous crossing logic into the unfolded integrated circuit design model to generate a second model; correlating outputs of the first model with outputs of the second model; applying one or more exclusive OR operations to the correlated outputs of the first model and the second model; and performing, by the data processing system, sequential equivalence checking on the first model and second model utilizing the applied one or more exclusive OR operations, wherein the asynchronous crossing logic comprises skewing logic for selecting a phase difference between clocks of asynchronous domains of asynchronous crossings in the unfolded integrated circuit design. - View Dependent Claims (2, 3, 4)
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5. A method, in a data processing system, for performing asynchronous verification of an integrated circuit design, comprising:
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receiving a first model of the integrated circuit design; unfolding paths within the first model that have asynchronous crossings to generate an unfolded integrated circuit design model; inserting asynchronous crossing logic into the unfolded integrated circuit design model to generate a second model; correlating outputs of the first model with outputs of the second model; applying one or more exclusive OR operations to the correlated outputs of the first model and the second model; performing sequential equivalence checking on the first model and second model utilizing the applied one or more exclusive OR operations; determining, based on outputs of the one or more exclusive OR operations due to the sequential equivalence checking, whether the asynchronous crossings of the integrated circuit design are verified or not verified; generating an output indicative of whether the asynchronous crossings of the integrated circuit design are verified or not verified based on results of the determination; and performing, by the data processing system, a failure analysis to determine if a failure of the asynchronous crossings is a real failure or a false failure in response to determining that the asynchronous crossings of the integrated circuit design are not verified. - View Dependent Claims (6, 7)
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8. An apparatus, comprising:
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a processor; and a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to; receive a first model of the integrated circuit design; unfold paths within the first model that have asynchronous crossings to generate an unfolded integrated circuit design model; insert asynchronous crossing logic into the unfolded integrated circuit design model to generate a second model; correlate outputs of the first model with outputs of the second model; apply one or more exclusive OR operations to the correlated outputs of the first model and the second model; and perform sequential equivalence checking on the first model and second model utilizing the applied one or more exclusive OR operations, wherein the asynchronous crossing logic comprises skewing logic for selecting a phase difference between clocks of asynchronous domains of asynchronous crossings in the unfolded integrated circuit design. - View Dependent Claims (9, 10, 11)
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12. An apparatus, comprising:
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a processor; and a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to; receive a first model of the integrated circuit design; unfold paths within the first model that have asynchronous crossings to generate an unfolded integrated circuit design model; insert asynchronous crossing logic into the unfolded integrated circuit design model to generate a second model; correlate outputs of the first model with outputs of the second model; apply one or more exclusive OR operations to the correlated outputs of the first model and the second model; perform sequential equivalence checking on the first model and second model utilizing the applied one or more exclusive OR operations; determine, based on outputs of the one or more exclusive OR operations due to the sequential equivalence checking, whether the asynchronous crossings of the integrated circuit design are verified or not verified; generate an output indicative of whether the asynchronous crossings of the integrated circuit design are verified or not verified based on results of the determination; and perform a failure analysis to determine if a failure of the asynchronous crossings is a real failure or a false failure in response to determining that the asynchronous crossings of the integrated circuit design are not verified. - View Dependent Claims (13, 14)
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15. A computer program product comprising a computer recordable storage device having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:
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receive a first model of the integrated circuit design; unfold paths within the first model that have asynchronous crossings to generate an unfolded integrated circuit design model; insert asynchronous crossing logic into the unfolded integrated circuit design model to generate a second model; correlate outputs of the first model with outputs of the second model; apply one or more exclusive OR operations to the correlated outputs of the first model and the second model; and perform sequential equivalence checking on the first model and second model utilizing the applied one or more exclusive OR operations, wherein the asynchronous crossing logic comprises skewing logic for selecting a phase difference between clocks of asynchronous domains of asynchronous crossings in the unfolded integrated circuit design. - View Dependent Claims (16, 17, 18)
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19. A computer program product comprising a computer recordable storage device having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:
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receive a first model of the integrated circuit design; unfold paths within the first model that have asynchronous crossings to generate an unfolded integrated circuit design model; insert asynchronous crossing logic into the unfolded integrated circuit design model to generate a second model; correlate outputs of the first model with outputs of the second model; apply one or more exclusive OR operations to the correlated outputs of the first model and the second model; perform sequential equivalence checking on the first model and second model utilizing the applied one or more exclusive OR operations determine, based on outputs of the one or more exclusive OR operations due to the sequential equivalence checking, whether the asynchronous crossings of the integrated circuit design are verified or not verified; generate an output indicative of whether the asynchronous crossings of the integrated circuit design are verified or not verified based on results of the determination; and perform a failure analysis to determine if a failure of the asynchronous crossings is a real failure or a false failure in response to determining that the asynchronous crossings of the integrated circuit design are not verified. - View Dependent Claims (20, 21)
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Specification