Gate dielectric/isolation structure formation in high/low voltage regions of semiconductor device

• US 7,883,955 B2
• Filed: 04/06/2010
• Issued: 02/08/2011
• Est. Priority Date: 11/05/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Okumura, Yoichi
• Primary Examiner(s): Fahmy; Wael M
• Assistant Examiner(s): SALERNO, SARAH KATE
• Application Number:
  US12/755,320
• Publication Number:
  US 20100197091A1
• Time in Patent Office: 308 Days
• Field of Search: 438/218, 438/400, 257/E21.545, 257/E21.632
• US Class Current: 438/218
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body

Abstract

A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr1) that is formed simultaneously in a first thermal oxidation process together with the formation of LOCOS isolation structures (3) for element seaaration of low voltage PMOS and NMOS transistors (Tr3, Tr4), and has a thinner gate dielectric layer (gate-insulation film 25 of, e.g., 7 nm) for a high voltage NMOS transistor (Tr2) that is formed simultaneously in a second thermal oxidation process together with the formation of gate dielectric layers (gate-insulation films 33, 42) of low voltage PMOS and NMOS transistors (Tr3, Tr4).

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a layer of insulating material over high voltage PMOS, high voltage NMOS, and low voltage MOS transistor formation regions of a semiconductor substrate;

patterning the layer of insulating material to form first isolation structures for the high voltage PMOS and for the high voltage NMOS transistor formation regions;

forming and patterning a layer of masking material to cover channel regions of the high voltage NMOS and low voltage MOS transistor formation regions;

with the channel regions of the high voltage NMOS and low voltage MOS transistor formation regions covered, conducting a first thermal oxidation to form a first gate dielectric layer over a channel region of the high voltage PMOS transistor formation region and to simultaneously form second isolation structures for the low voltage MOS transistor formation region;

following the first thermal oxidation, removing the patterned layer of masking material from the channel regions of the high voltage NMOS and low voltage MOS transistor formation regions; and

following removal of the patterned layer of masking material, conducting a second thermal oxidation to form second gate dielectric layers simultaneously over the channel regions of the high voltage NMOS and low voltage MOS transistor formation regions;

the second gate dielectric layers being formed to a thickness less than the thickness to which the first gate dielectric layer is formed.

2. The method of claim 1, wherein the semiconductor substrate comprises silicon and wherein the first and second dielectric layers comprise silicon oxide.

3. The method of claim 2, wherein the layer of masking material comprises silicon nitride.

4. The method of claim 3, wherein the layer of insulating material comprises silicon oxide.

5. The method of claim 4, wherein the second thermal oxidation is performed at a lower temperature and for a substantially shorter time than the first thermal oxidation.

6. The method of claim 5, wherein the second thermal oxidation is performed at 850°

C. for about 7 minutes and the first thermal oxidation is performed at 900°

C. for about 300 minutes.

7. The method of claim 4, wherein the first gate dielectric layer and second isolation structures are formed to a thickness of about 400 nm and the second gate dielectric layers are formed to a thickness of about 14 nm.

8. The method of claim 4, further comprising forming a layer of gate electrode material comprising polysilicon over the first and second gate dielectric layers.

9. A method of manufacturing a semiconductor device, comprising:

forming a layer of insulating material over high voltage PMOS, high voltage NMOS, low voltage PMOS and low voltage MOS transistor formation regions of a semiconductor substrate;

patterning the layer of insulating material to form first isolation structures for the high voltage PMOS and for the high voltage NMOS transistor formation regions;

forming and patterning a layer of masking material to cover channel regions of the high voltage NMOS, low voltage PMOS and low voltage NMOS transistor formation regions;

with the channel regions of the high voltage NMOS, low voltage PMOS and low voltage NMOS transistor formation regions covered, conducting a first thermal oxidation to form a first gate dielectric layer over a channel region of the high voltage PMOS transistor formation region and to simultaneously form second isolation structures for the low voltage PMOS and low voltage NMOS transistor formation regions;

following the first thermal oxidation, removing the patterned layer of masking material from the channel regions of the high voltage NMOS, low voltage PMOS and low voltage NMOS transistor formation regions; and

following removal of the patterned layer of masking material, conducting a second thermal oxidation to form second gate dielectric layers simultaneously over the channel regions of the high voltage NMOS, low voltage PMOS and low voltage NMOS transistor formation regions;

the second gate dielectric layers being formed to a thickness less than the thickness to which the first gate dielectric layer is formed.

10. A method of manufacturing a semiconductor device, comprising:

forming a silicon oxide insulating film over high voltage PMOS, high voltage NMOS, low voltage PMOS and low voltage MOS transistor formation regions of a semiconductor substrate;

patterning the silicon oxide insulating film to form first element separation isolation structures for the high voltage PMOS and for the high voltage NMOS transistor formation regions;

forming and patterning a silicon nitride film as a mask layer to cover first channel regions of the high voltage NMOS, low voltage PMOS and low voltage NMOS transistor formation regions, leaving a second channel region of the high voltage PMOS transistor formation region exposed;

with the patterned silicon nitride film covering the first channel regions, conducting a first thermal oxidation to grow a first silicon oxide gate dielectric layer over the second channel region and to simultaneously form LOCOS second element separation isolation structures in the low voltage PMOS and low voltage NMOS transistor formation regions;

following the first thermal oxidation, removing the patterned silicon nitride film; and

with the patterned silicon nitride film removed, conducting a second thermal oxidation to grow second silicon oxide gate dielectric layers simultaneously over the channel regions of the high voltage NMOS, low voltage PMOS and low voltage NMOS transistor formation regions;

the second silicon oxide gate dielectric layers being formed to a thickness less than the thickness to which the first silicon oxide gate dielectric layer is formed.

11. The method of claim 10, further comprising forming a layer of polysilicon gate electrode material over the first and second silicon oxide gate dielectric layers.

12. The method of claim 11, further comprising patterning the layer of polysilicon gate electrode material to form gate electrodes;

and implanting source/drain regions adjacent the gate electrodes.

13. The method of claim 12, further comprising implanting back gate regions adjacent source regions in the high voltage PMOS and high voltage NMOS transistor formation regions.

14. The method of claim 13, wherein the substrate comprises p-doped semiconductor material;

and further comprising forming a n-type well in the high voltage PMOS transistor formation region;

forming a p-type drain region in the n-type well;

forming an n-type drain region in the high voltage NMOS transistor formation region; and

forming an n-type well in the low voltage PMOS transistor formation region.

15. The method of claim 14, wherein forming the first element separation isolation structures includes forming first element separation isolation structures over a portion of the p-type drain region in the high voltage PMOS transistor formation region and over a portion of the n-type drain region in the high voltage NMOS transistor formation region.

16. The method of claim 15, wherein implanting the source/drain regions comprises implanting a drain region in another portion of the p-type drain region in the high voltage PMOS transistor formation region and implanting a drain region in another portion of the n-type drain region in the high voltage NMOS transistor formation region.