Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods

• US 7,884,015 B2
• Filed: 12/06/2007
• Issued: 02/08/2011
• Est. Priority Date: 12/06/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sulfridge, Marc
• Primary Examiner(s): Garber; Charles D
• Assistant Examiner(s): Junge; Bryan R
• Application Number:
  US11/951,751
• Publication Number:
  US 20090146312A1
• Time in Patent Office: 1,160 Days
• Field of Search: 438/618, 438/667, 438/780, 257/E21.575, 257/E21.597
• US Class Current: 438/667
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment, for example, is directed to a method of processing a microelectronic workpiece including a semiconductor substrate having a plurality of microelectronic dies. The individual dies include integrated circuitry and a terminal electrically coupled to the integrated circuitry. The method can include forming a first opening in the substrate from a back side of the substrate toward a front side and in alignment with the terminal. The first opening has a generally annular cross-sectional profile and separates an island of substrate material from the substrate. The method can also include depositing an insulating material into at least a portion of the first opening, and then removing the island of substrate material to form a second opening aligned with at least a portion of the terminal. In several embodiments, the method may include constructing an electrically conductive interconnect in at least a portion of the second opening and in electrical contact with the terminal.

Claims

1. A method of processing a microelectronic workpiece including a semiconductor substrate having a plurality of microelectronic dies, the individual dies including integrated circuitry and a terminal electrically coupled to the integrated circuitry, the method comprising:

forming a first opening in the substrate from a back side of the substrate toward a front side of the substrate and in alignment with the terminal, the first opening having a generally annular cross-sectional profile and separating an island of substrate material from the substrate, and wherein the island of substrate material has an upper surface that extends outwardly past the back side of the substrate;

depositing an insulating material into at least a portion of the first opening; and

removing the island of substrate material after depositing the insulating material and forming a second opening aligned with at least a portion of the terminal, wherein the second opening does not extend completely through the terminal.

2. The method of claim 1, further comprising constructing an electrically conductive interconnect in at least a portion of the second opening and in electrical contact with the terminal.

3. The method of claim 1 wherein depositing an insulating material into at least a portion of the first opening comprises depositing a polymer material into the first opening.

4. The method of claim 3 wherein depositing an insulating material into at least a portion of the first opening comprises depositing a filled epoxy material into the first opening.

5. The method of claim 1 wherein depositing an insulating material into at least a portion of the first opening comprises depositing a polymer material having a coefficient of thermal expansion (CTE) at least generally similar to the CTE of the substrate.

6. The method of claim 1 wherein the substrate further comprises a dielectric layer between the terminal and the front side of the substrate, and wherein:

forming a first opening in the substrate comprises forming a blind hole in the substrate from the back side of the substrate to the dielectric layer; and

removing the island of substrate material to form a second opening in alignment with the terminal further comprises removing at least a portion of the dielectric layer after removing the island of substrate material to expose at least a portion of the terminal.

7. The method of claim 1 wherein removing the island of substrate material comprises removing the island with a wet etching process.

8. The method of claim 1 wherein depositing an insulating material into at least a portion of the first opening comprises:

at least generally filling the first opening with the insulating material; and

covering the exposed portions of the back side of the substrate with the insulating material.

9. The method of claim 1 wherein forming a first opening in the substrate comprises:

applying and patterning a first mask layer on the back side of the substrate and forming a first mask portion at least partially aligned with the terminal;

etching the back side of the substrate with a first etching process;

applying and patterning a second mask layer on the back side of the substrate and forming a third opening in the second mask layer, wherein the third opening is an annulus that completely surrounds the first mask portion and the corresponding portion of the substrate, and wherein an outer periphery portion of the third opening is inboard of an outer periphery portion of the corresponding terminal; and

etching the back side of the substrate with a second etching process to form the first opening in the substrate from the back side of the substrate toward the front side, wherein the first opening has a cross-sectional profile at least approximately identical to the cross-sectional profile of the third opening; and

removing the remaining portions of the first mask layer and the second mask layer from the substrate before depositing the insulating material into at least a portion of the first opening.

10. The method of claim 1, further comprising:

adhesively attaching the front side of the substrate to a support member;

removing material from back side of the substrate to thin the substrate before forming the first opening; and

removing the substrate from the support member after constructing the electrically conductive interconnect.

11. The method of claim 1 wherein:

forming a first opening in the substrate comprises forming a plurality of first openings in the back side of each die and in alignment with corresponding terminals, wherein the first openings are generally circular rings surrounding a core of substrate material, and wherein the first openings do not extend through the terminals;

depositing an insulating material comprises disposing a polymeric dielectric material in the first openings; and

removing the island of substrate material comprises removing the cores of substrate material within the first openings after disposing the polymeric dielectric material in the first openings, wherein removing the cores of substrate material forms a plurality of blind vias in alignment with corresponding terminals.

12. The method of claim 11, further comprising planarizing the back side of the dies to remove the dielectric material outside of the openings after filling the openings with the dielectric material.

17. The method of claim 5 wherein depositing a polymer material comprises depositing a polymer material having a CTE of from about 22 to 30 ppm/°

C.

18. The method of claim 10 wherein removing material from back side of the substrate to thin the substrate comprises thinning the substrate to a thickness of about 100 microns.

13. A method of processing a semiconductor substrate including a via site and a plug site within the via site, the method comprising:

masking the plug site and a region at least partially surrounding the via site at a back side of the substrate, wherein masking includes exposing a perimeter of the via site;

etching the substrate after masking and defining a plug at the plug site, wherein the plug is at least partially aligned with an electrical contact on the substrate, and wherein the plug has an upper surface that extends outwardly beyond an elevation of the region;

dispensing insulation onto the substrate and between the plug and the substrate; and

removing the plug.

14. The method of claim 13 wherein masking the plug site comprises masking the plug site with a second mask, and wherein the method further comprises:

masking the plug site with a first mask before masking the plug site with the second mask, wherein masking the plug site with the first mask includes exposing the region; and

etching the substrate using the first mask before masking the plug site with the second mask.

15. A method of manufacturing a semiconductor substrate having a plurality of microelectronic imaging dies, the individual imaging dies including integrated circuitry, an image sensor electrically coupled to the integrated circuitry, and a terminal electrically coupled to the integrated circuitry, the method comprising:

disposing a polymer material into a first blind opening in a back side of the substrate, wherein the first blind opening is an annulus superimposed relative to the terminal, and wherein the annulus has a first cross-sectional dimension less than a second cross-sectional dimension of the terminal;

etching a core of substrate material surrounded by the polymer material within the annulus and forming a second blind opening in the back side of the substrate, wherein the second blind opening does not extend through the terminal, and wherein the core of substrate material has an upper surface that extends outwardly past the back side of the substrate; and

forming a through-substrate interconnect in at least a portion of the second blind opening and in electrical contact with the terminal.

16. A method of processing a microelectronic workpiece including a semiconductor substrate having a plurality of microelectronic dies, the individual dies including integrated circuitry and a terminal electrically coupled to the integrated circuitry, the method comprising:

forming a first opening in the substrate from a back side of the substrate toward a front side of the substrate and in alignment with the terminal, the first opening having a generally annular cross-sectional profile and separating an island of substrate material from the substrate, wherein forming the first opening in the substrate comprises—

applying and patterning a first mask layer on the back side of the substrate and forming a first mask portion at least partially aligned with the terminal;

etching the back side of the substrate with a first etching process;

applying and patterning a second mask layer on the back side of the substrate and forming a third opening in the second mask layer, wherein the third opening is an annulus that completely surrounds the first mask portion and the corresponding portion of the substrate, and wherein an outer periphery portion of the third opening is inboard of an outer periphery portion of the corresponding terminal; and

etching the back side of the substrate with a second etching process to form the first opening in the substrate from the back side of the substrate toward the front side, wherein the first opening has a cross-sectional profile at least approximately identical to the cross-sectional profile of the third opening; and

removing the remaining portions of the first mask layer and the second mask layer from the substrate before depositing the insulating material into at least a portion of the first opening;

depositing an insulating material into at least a portion of the first opening after removing the remaining portions of the first mask layer and the second mask layer from the substrate; and

removing the island of substrate material after depositing the insulating material and forming a second opening aligned with at least a portion of the terminal, wherein the second opening does not extend completely through the terminal.