Nonvolatile semiconductor storage device, and method for controlling nonvolatile semiconductor storage device

• US 7,884,417 B2
• Filed: 10/02/2008
• Issued: 02/08/2011
• Est. Priority Date: 10/03/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Arai, Fumitaka, Mizukami, Makoto
• Primary Examiner(s): Le; Vu A
• Application Number:
  US12/244,307
• Publication Number:
  US 20090097309A1
• Time in Patent Office: 859 Days
• Field of Search: 257/324, 365/185.17, 365/185.05
• US Class Current: 257/324
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.

Claims

1. A nonvolatile semiconductor storage device comprising:

a substrate;

a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers using a marker layer;

a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and

a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.

2. The nonvolatile semiconductor storage device according to claim 1,

wherein each of the conductor layers forms a memory cell transistor with the charge accumulation film and the semiconductor pillar.

3. The nonvolatile semiconductor storage device according to claim 2,

wherein each of the conductor layers is serving as a control electrode of the memory cell transistor,

the charge accumulation film is serving as a data holding member of the memory cell transistor, and

the semiconductor pillar is serving as a channel-forming member of the memory cell transistor.

4. The nonvolatile semiconductor storage device according to claim 1,

wherein the marker layer is configured to be distinguishable from the other layers of the conductor layers and the insulation layers in an observation using by SEM or TEM.

5. The nonvolatile semiconductor storage device according to claim 1,

wherein the marker layer is formed of a material different from those of the other layers of the conductor layers and the insulation layers.

6. The nonvolatile semiconductor storage device according to claim 1,

wherein the marker layer is formed by changing at least one layer of the plurality of insulation layers, and

the marker layer is formed to have a thickness different from those of the other layers of the insulation layers.

7. The nonvolatile semiconductor storage device according to claim 1,

wherein the marker layer is formed by changing at least one layer of the plurality of conductor layers, and

the marker layer is formed to have a thickness different from those of the other layers of the conductor layers.

8. The nonvolatile semiconductor storage device according to claim 1,

wherein the marker layer is formed by changing at least one layer of the plurality of conductor layers, and

the marker layer forms a control gate transistor with the semiconductor pillar.

9. The nonvolatile semiconductor storage device according to claim 1,

wherein the charge accumulation film includes an ONO film that is formed of a silicon oxide film, a silicon nitride film and a silicon oxide film.

10. The nonvolatile semiconductor storage device according to claim 1,

wherein the charge accumulation film is formed of a gate insulation film, a charge accumulation gate electrode and an inter-electrode insulation film.

11. The nonvolatile semiconductor storage device according to claim 1,

wherein the marker film has a multi-layer structure.