High density interconnect system having rapid fabrication cycle

• US 7,884,634 B2
• Filed: 01/15/2009
• Issued: 02/08/2011
• Est. Priority Date: 05/27/1999
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Verigy Limited (Advantest Corporation)
• Inventors: Mok, Sammy, Chong, Fu Chiung, Swiatowiec, Frank John, Parekh, Nitin, Litza, Anna, Shan, Zhaohui, Kao, Andrew, Modlin, Douglas, McKay, Douglas
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): Nguyen; Tung X
• Application Number:
  US12/354,520
• Publication Number:
  US 20090153165A1
• Time in Patent Office: 754 Days
• Field of Search: 324/754, 324761-762, 324/765, 324/158.1, 298/25, 298/32, 298/30, 298/42, 257/48, 438 14- 18
• US Class Current: 324/762.02
• CPC Class Codes: G01R 1/073 Multiple probes
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49222 forming array of contacts or terminals

Abstract

An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.

Claims

1. An apparatus, comprising:

a probe card interface assembly, comprising

a motherboard substrate having a lower surface, an upper surface opposite the lower surface, and a plurality of electrical conductors extending from the upper surface to the lower surface, wherein the electrical conductors form a pattern of electrical connections on the lower surface of the motherboard substrate, and

a probe chip mounting system affixed to the motherboard comprising

at least one substrate and having a motherboard interface surface and a probe chip assembly mounting surface opposite the motherboard interface surface, and

a plurality of electrical conductors corresponding to the pattern of electrical connections on the bottom surface of said motherboard substrate, the electrical conductors extending from the motherboard interface surface to the probe chip assembly mounting surface; and

a probe chip assembly mounted to the probe card interface assembly, the probe chip assembly comprising a probe chip substrate having a probing surface and a mounting surface opposite the probing surface, and a plurality of probe springs extending from said probing surface for providing electrical connections to at least one integrated circuit device on a semiconductor wafer, said probe springs having electrical connections to a plurality of standard connections on the mounting surface, said standard connections corresponding to said pattern of electrical connections on said bottom surface of said motherboard substrate;

wherein a probe chip assembly mounting reference plane is defined by at least three points between the lower surface of the motherboard substrate and the semiconductor wafer, wherein the probe chip assembly mounting reference plane is adjustable to be coplanar to the probe chip assembly mounting surface of the probe card interface assembly based on measured data of the probe card interface assembly.

2. The apparatus of claim 1, wherein the motherboard substrate comprises a multi-layered printed wiring board.

3. The apparatus of claim 1, wherein the at least one substrate comprises any of a ceramic, a multilayered ceramic, and a co-fired ceramic.

4. The apparatus of claim 1, wherein the probe springs are plated.

7. The apparatus of claim 1, further comprising:

a planarity adjustment mechanism for adjusting planarity between the probe chip mounting system and the lower surface of the motherboard substrate.

8. The apparatus of claim 1, wherein the probe chip assembly mounting reference plane comprises any of points that coincide with a real surface within the probe chip mounting system, or points that comprises a virtual defined plane that is parallel to the lower surface of the motherboard substrate.

5. A method of production of a rapid cycle time customizable probe card for testing semiconductor wafers, comprising the steps of:

providing a plurality of customizable components, each having a rapid design and fabrication process cycle time;

providing a plurality of standard components, wherein design and fabrication process cycle time of at least one of said standard components is longer than the rapid design and fabrication process cycle time for the customizable components; and

assembling and testing a probe card from both the customizable components and the standard components, wherein the probe card assembly and test cycle time is no greater than that of the longest of the cycle times for the customizable components.

6. The method of claim 5,

wherein the customizable components having rapid cycle times comprise any of a mother board and a probe chip assembly;

and

wherein the standard components having cycle times that may be longer than those of the mother board and probe chip comprise any of a probe tip support substrate and at least one interposer.