Method and system for defining and controlling algorithmic elements in a graphics display system

• US 7,884,817 B2
• Filed: 09/02/2004
• Issued: 02/08/2011
• Est. Priority Date: 03/07/2000
• Status: Expired due to Fees

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Toelle, Michael A., Boyd, Charles N.
• Primary Examiner(s): Wu; Xiao M
• Assistant Examiner(s): Tseng; Charles
• Application Number:
  US10/934,274
• Publication Number:
  US 20050027682A1
• Time in Patent Office: 2,350 Days
• Field of Search: 345418-419, 345/581, 345/619
• US Class Current: 345/418
• CPC Class Codes: G06T 15/005 General purpose rendering architectures

Abstract

An API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are also a set of algorithmic elements that are provided in connection with the API that have already been programmed for the developer, that are downloadable to the programmable chip for improved performance. Thus, a developer may download preexisting API objects to a 3D graphics chip. A developer adheres to a specific format for packing up an algorithmic element, or set of instructions, for implementation by a 3D graphics chip. The developer packs the instruction set into an array of numbers, by referring to a list of ‘tokens’ understood by the 3D graphics chip. This array of numbers in turn is mapped correctly to the 3D graphics chip for implementation of the algorithmic element by the 3D graphics chip.

Claims

1. A graphics chip having stored thereon computer-executable instructions, the computer-executable instructions for specifying a declaration array for a procedural shader, the declaration array setting forth procedural shader instructions accessible by a developer through an application programming interface (API) and comprising:

a plurality of DWORDs wherein each of the plurality of DWORDs includes at least one token selected from a list of tokens that is interpretable by the graphics chip and provides an instruction to be performed by the procedural shader; and

at least an algorithmic element that is an instruction set packed into the plurality of DWORDs by the API and represents an already programmed algorithm that provides functionality for the procedural shader below or inside the API, the algorithmic element being accessible by a developer via the API and being formed by mapping the plurality of DWORDs to corresponding locations of the procedural shader for implementing the instructions for the at least one token.

2. A graphics chip according to claim 1, wherein the plurality of DWORDs is structured as an array.

3. A graphics chip according to claim 1, wherein the plurality of DWORDs includes data representative of assignments of procedural shader input registers to data stream elements, whereby the assignments bind a specific vertex register to a single vertex stream element within a vertex stream and wherein a vertex stream element is identified by a byte offset within the stream and a type.

4. A graphics chip according to claim 3, wherein the type specifies an arithmetic data type and a dimensionality.

5. A graphics chip according to claim 3, wherein a stream data element that is less than four values is expanded to consist of four values.

6. A graphics chip according to claim 3, wherein data streams include data which is not loaded into a vertex register, thus allowing data which is not used by the procedural shader to exist in the vertex stream, whereby the skipped data is defined by a count of DWORDs to skip over.

7. A graphics chip according to claim 1, wherein the plurality of DWORDs includes data representative of assignments of procedural shader input registers to implicit data from a primitive tessellator, thereby controlling the loading of vertex data, which is generated during a primitive tessellation process, prior to the vertex data being transmitted to the procedural shader.

8. A graphics chip according to claim 1, wherein the plurality of DWORDs includes data for loading into constant memory of the procedural shader at the time a procedural shader is set as the current procedural shader.

9. A graphics chip according to claim 8, wherein each token specifies values for at least one contiguous constant register of the procedural shader, thereby allowing the procedural shader to update an arbitrary subset of the constant memory.

10. A graphics chip according to claim 1, wherein the at least one token includes at least one of (1) an NOP token wherein an NOP token is ignored during parsing of the declaration array, (2) a stream selector token, (3) a stream data definition token providing a mapping to vertex input memory, (4) a vertex input memory from tessellator token for use in connection with assigning vertex input memory from a tessellator, (5) a constant memory token for use in connection with loading constant memory of the procedural shader, (6) an extension token, (7) a reserved token and (8) an end of array token specifying the end of the declaration array.

11. A graphics chip according to claim 10, wherein the NOP token, the stream selector token, the stream data definition token, the vertex input memory from tessellator token, the reserved token and the end of array token are single DWORD tokens.

12. A graphics chip according to claim 10, wherein streams are allowed to include data which is not loaded into a vertex register, thus allowing data which is not used for the procedural shader to exist in the vertex stream, whereby the skipped data is defined by a count of DWORDs to skip over.

13. A graphics chip according to claim 1, wherein the computer-executable instructions further comprise computer-executable instructions for receiving the plurality of DWORDs in respective data containers in parallel.

14. A graphics chip according to claim 1, wherein the computer-executable instructions further comprise computer-executable instructions for receiving tokens in respective data containers in parallel.

15. A video card comprising:

a video memory that stores input data stream elements; and

a graphics chip having stored thereon computer-executable instructions, the computer-executable instructions for specifying a declaration array for a procedural shader that processes the input data stream elements, the declaration array setting forth procedural shader instructions accessible by a developer through an application programming interface (API) and comprising;

a plurality of DWORDs wherein each of the plurality of DWORDs includes at least one token selected from a list of tokens that is interpretable by the graphics chip and provides an instruction to be performed by the procedural shader; and

at least an algorithmic element that is an instruction set packed into the plurality of DWORDs by the API that represents an already programmed algorithm that provides functionality for the procedural shader below or inside the API, the algorithmic element being accessible by a developer via the API and being formed by mapping the plurality of DWORDs to corresponding locations of the procedural shader for implementing the instructions for the at least one token.

16. A video card according to claim 15, wherein the plurality of DWORDs is structured as an array.

17. A video card according to claim 15, wherein the plurality of DWORDs includes data representative of assignments of procedural shader input registers to data stream elements, whereby the assignments bind a specific vertex register to a single vertex stream element within a vertex stream and wherein a vertex stream element is identified by a byte offset within the stream and a type.

18. A video card according to claim 17, wherein data streams include data which is not loaded into a vertex register, thus allowing data which is not used by the procedural shader to exist in the vertex stream, whereby the skipped data is defined by a count of DWORDs to skip over.

19. A video card according to claim 15, wherein the plurality of DWORDs includes data representative of assignments of procedural shader input registers to implicit data from a primitive tessellator, thereby controlling the loading of vertex data, which is generated during a primitive tessellation process, prior to the vertex data being transmitted to the procedural shader.

20. A video card according to claim 15, wherein the computer-executable instructions further comprise computer-executable instructions for receiving the plurality of DWORDs in respective data containers in parallel.