Non-volatile memory array with resistive sense element block erase and uni-directional write

• US 7,885,097 B2
• Filed: 07/10/2009
• Issued: 02/08/2011
• Est. Priority Date: 10/10/2008
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Lu, Yong, Li, Hai, Carter, Andrew John, Reed, Daniel S.
• Primary Examiner(s): HUR, JUNG H
• Application Number:
  US12/501,077
• Publication Number:
  US 20100091548A1
• Time in Patent Office: 578 Days
• Field of Search: 365/158, 365/171, 365/173, 365/148, 365/163, 365/189.16
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode

Abstract

In accordance with various embodiments, a column of non-volatile memory cells is connected between opposing first and second control lines. A fixed reference voltage is applied to the second control line. The memory cells are simultaneously programmed to a first resistive state by applying a first voltage to the first control line that is greater than the fixed reference voltage. Less than all of the memory cells are subsequently simultaneously programmed to a different, second resistive state by applying a second voltage to the first control line that is less than the fixed reference voltage, so that at the conclusion of the respective programming steps a first portion of the memory cells along said column are at the first resistive state and a second portion of the memory cells along said column are at the second resistive state.

Claims

1. An apparatus comprising an array of non-volatile memory cells arranged into a plurality of rows and a plurality of columns, each memory cell in the array comprising a switching device and a resistive sense element (RSE), wherein each of the memory cells in a selected column along a bit line direction are connected to a first control line supplied with a variable voltage and a second control line maintained at a fixed reference voltage, and wherein a plural number of the memory cells in the selected column less than all of the memory cells in the selected column are simultaneously programmed to a first resistive state by lowering the variable voltage of the first control line below the fixed reference voltage of the second control line and flowing respective body-drain currents through the associated switching devices of said plural number of memory cells, a remaining plural number of the memory cells along the selected column remaining at a different, second resistive state.

2. The apparatus of claim 1, wherein each of the memory cells in a selected row of the array is connected between respective bit lines and the second control line, and wherein less than all of the memory cells along the selected row are simultaneously programmed to a second resistive state by selective application of voltage to the associated bit lines greater than the fixed reference voltage.

3. A method comprising:

providing an array of non-volatile memory cells arranged into rows and columns, wherein each of the memory cells comprises a switching device in series with a resistive sense element (RSE), wherein each of the memory cells along a selected column along a bit line direction are connected between first and second control lines, and wherein a fixed reference voltage is continuously applied to the second control line;

programming the RSEs of all of the memory cells along the selected column simultaneously to a first resistive state by applying a first voltage to the first control line that is lower than the fixed reference voltage; and

subsequently programming a plurality of the RSEs less than all of the memory cells along the selected column simultaneously to a different, second resistive state by applying a second voltage to the first control line that is higher than the fixed reference voltage.

4. The method of claim 3, wherein the first control line is characterized as a bit line connected to the selected column, and wherein the providing step further comprises connecting the second control line between a source terminal of the switching devices in the memory cells along the selected column and a reference voltage source which continuously maintains the fixed reference voltage on the second control line during read and write operations upon the selected column.

5. The method of claim 3, wherein the first programming step comprises passing a body-drain current through the switching device to the RSE in each memory cell along the selected column to program the first resistive state, and wherein the second programming step comprises asserting a voltage on a gate of the switching device to flow current across a drain-source conductive path of the switching device in each memory cell of said less than all of the memory cells along the selected column to program the second resistive state.

6. The method of claim 3, wherein each RSE has a hard programming direction in which current flows to write the RSE to the first resistive state, and an easy programming direction in which current flows to write the RSE to the second resistive state, wherein the hard programming direction is opposite the easy programming direction.

7. The method of claim 3, wherein each RSE is characterized as a magnetic tunneling junction (MTJ) comprising a fixed reference layer with a magnetic orientation in a fixed direction and a free layer with a magnetic orientation in a selectively variable direction, and wherein the first resistive state orients the magnetic orientation of the free layer to be parallel with the magnetic orientation of the fixed reference layer.

8. The method of claim 3, wherein the fixed reference voltage is electrical ground.

9. The method of claim 3, wherein at the conclusion of the first and second programming states, a first portion of said memory cells along the selected column are programmed to the first resistive state and a remaining portion of said memory cells along the selected column are programmed to the second resistive state.

10. The method of claim 3, wherein the switching device of each memory cell is characterized as a metal oxide semiconductor field effect transistor (MOSFET) having respective drain, source and gate terminals, wherein the drain terminal is connected in series with the RSE of said cell, the source terminal is connected via the second control line to a fixed reference voltage source, and wherein the gate terminal is connected to a word line, wherein the first resistive state is written while a voltage of the word line is set to the fixed reference voltage, and wherein the second resistive state is written while a voltage of the word line is set to a level higher than the fixed reference voltage.

11. A method comprising:

connecting a column of non-volatile memory cells along a bit line direction between opposing first and second control lines;

applying a fixed reference voltage to the second control line;

simultaneously programming the memory cells along said column to a first resistive state by applying a first voltage to the first control line that is greater than the fixed reference voltage; and

subsequently simultaneously programming a plurality of the memory cells less than all of the memory cells along said column to a different, second resistive state by applying a second voltage to the first control line that is less than the fixed reference voltage, so that at the conclusion of the respective programming steps a first portion of the memory cells along said column are at the first resistive state and a second portion of the memory cells along said column are at the second resistive state.

12. The method of claim 11, in which the memory cells form a portion of an array of memory cells arranged into a plurality of rows and a plurality of columns, and the second control line is characterized as a source plane connected to each of the memory cells in said array.

13. The method of claim 11, in which each memory cell along the column comprises a switching device connected in series with a resistive sense element (RSE) between the first and second control lines, each switching device comprising a source terminal, a drain terminal, and a gate terminal.

14. The method of claim 13, wherein the RSEs of the first portion of memory cells are programmed to the first resistive state by raising a voltage of the first control line to a level above the fixed reference voltage and by raising a gate control voltage of the gate terminals of the switching devices of said first portion to a level above the fixed reference voltage to provide a drain-source conductive path through the switching device.

15. The method of claim 13, wherein the RSEs of the second portion of memory cells are programmed to the second resistive state by lowering a voltage of the first control line to a level below the fixed reference voltage and by setting the gate terminals of the switching devices of said second portion to a level nominally equal to the fixed reference voltage, thereby inducing a body-drain current to flow through said switching devices.

16. The method of claim 11, in which each of the memory cells is characterized as a spin-torque transfer random access memory (STRAM) cell.

17. The method of claim 11, in which each memory cell comprises a magnetic tunneling junction (MTJ) comprising a fixed reference layer with a magnetic orientation in a fixed direction and a free layer with a magnetic orientation in a selectively variable direction, wherein the first resistive state orients the magnetic orientation of the free layer to be parallel with the magnetic orientation of the fixed reference layer, and the second resistive state orients the magnetic orientation of the free layer to be antiparallel with the magnetic orientation of the fixed reference layer.

18. The memory cell of claim 11, wherein the fixed reference voltage is electrical ground.