Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages

• US 7,885,112 B2
• Filed: 09/07/2007
• Issued: 02/08/2011
• Est. Priority Date: 09/07/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Mokhlesi, Nima, Fong, Yupin Kawing, Li, Yan
• Primary Examiner(s): Luu; Pho M
• Assistant Examiner(s): BUI, THA-O H
• Application Number:
  US11/852,229
• Publication Number:
  US 20090067244A1
• Time in Patent Office: 1,250 Days
• Field of Search: 365/185.17, 365/185.26, 365/185.12, 365/235, 365/185.02, 365/185.017, 365/185.19
• US Class Current: 365/185.12
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5647 Multilevel memory with bit inversion arrangement
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to floating gate coupling among neighboring cells. Randomization from page to page helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. In another embodiment, randomization is implemented both within a page and between pages. The scrambling or randomization may be predetermined, or code generated pseudo randomization or user driven randomization in different embodiments. These features are accomplished within the limited resource and budget of the integrated-circuit memory chip.

Claims

1. An integrated-circuit memory chip, comprising:

an array of nonvolatile memory cells accessible page by page, each page being a group of memory cells, each memory cell of the group being in a column of the array and along a row accessible by a common word line;

a sequence of non-identical starting column positions so that each page to be programmed has an associated starting column position;

an address generator for generating an address for the associated starting column position;

a set of data latches associated with each column responsive to the address generator for staging data to be programmed into each page, the staged data starting from the associated starting column position and wrapping around until the page is filled; and

a programming circuit to program in parallel the staged data into each page.

2. The memory chip as in claim 1, wherein the pages are numbered consecutively and the starting column position associated with a page is a function of the page number.

3. The memory chip as in claim 2, wherein the function is such that the column position is modulo of the number of cells in the group plus a predetermined number.

4. The memory chip as in claim 3, wherein the predetermined number is zero.

5. The memory chip as in claim 1, further comprising:

a pseudo random generator; and

the sequence of non-identical starting column positions is generated on-chip by the pseudo random generator.

6. The memory chip as in claim 5, wherein:

the pseudo random generator is also responsive to a timing triggered by an event external to the memory chip; and

the sequence of non-identical starting column positions is also a function the timing.

7. The memory chip as in claim 1, further comprising:

first and second encodings for each page of data to be programmed;

a sequence of polarity bits, one for each page; and

an encoder to encode the page of data with either first or second encoding according to whether the polarity bit for the page is in a first or second state.

8. The memory chip as in claim 1, wherein the memory cells of the array are organized in a NAND architecture.

9. An integrated-circuit memory chip, comprising:

an array of nonvolatile memory cells accessible page by page, each page being a group of memory cells, each memory cell of the group being in a column of the array and along a row accessible by a common word line;

first and second encodings for each set of columns in which data is to be programmed;

a sequence of non-identical polarity bits, one for a set of columns of a page;

an encoder to encode the data bits associated with each set of columns with either first or second encoding according to whether the polarity bit for the set of columns is in a first or second state; and

a programming circuit to program in parallel the encoded data into each page.

10. The memory chip as in claim 9, wherein the first encoding is to leave the data bit associated with each column unchanged and the second encoding is to flip the data bit.

11. The memory chip as in claim 9, further comprising:

a pseudo random generator; and

wherein

the sequence of polarity bits is generated by the pseudo random generator.

12. In an integrated-circuit memory chip having an array of nonvolatile memory cells accessible page by page, each page being a group of memory cells, each memory cell of the group being in a column of the array and along a row accessible by a common word line, a method for programming data into the array comprising:

generating on-chip a sequence of non-identical starting column positions so that each page to be programmed has an associated starting column position;

staging data to be programmed into each page by starting from the associated starting column position and wrapping around until the page is filled; and

programming the staged data in parallel into each page.

13. The method as in claim 12, wherein the pages are numbered consecutively and the starting column position associated with a page is a function of the page number.

14. The method as in claim 13, wherein the function is such that the column position is modulo of the number of cells in the group plus a predetermined number.

15. The method as in claim 14, wherein the predetermined number is zero.

16. The method as in claim 12, wherein:

the sequence of non-identical starting column positions is generated on-chip by a pseudo random generator.

17. The method as in claim 16, wherein:

the pseudo random generator is also responsive to a timing triggered by an event external to the memory chip; and

the sequence of non-identical starting column positions is also a function the timing.

18. The method as in claim 17, wherein the external event is initiated by a user of the memory chip.

19. The method as in claim 17, wherein the external event is initiated by an external memory controller.

20. The method as in claim 12, further comprising:

providing first and second encodings for each page of data to be programmed;

generating on-chip a sequence of non-identical polarity bits, one for each page; and

encoding the page of data with either first or second encoding according to whether the polarity bit for the page is in a first or second state.

21. In an integrated-circuit memory chip having an array of nonvolatile memory cells accessible page by page, each page being a group of memory cells, each memory cell of the group being in a column of the array and along a row accessible by a common word line, a method for programming data into the array comprising:

providing first and second encodings for each set of columns in which data is to be programmed;

generating on-chip a sequence of non-identical polarity bits, one for each set of columns of a page;

encoding the data bit associated with each set of columns with either first or second encoding according to whether the polarity bit for each set of columns is in a first or second state; and

programming in parallel the encoded data into each page.

22. The method as in claim 21, wherein the first encoding is to leave the data bits associated with each set of columns unchanged and the second encoding is to flip the data bits.

23. The method as in claim 21, wherein the sequence of non-identical polarity bits is generated on-chip by a pseudo random generator.